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Searched refs:IOMUXD_QSPI1A_DQS_sw_config_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_ca53.h50225 #define IOMUXD_QSPI1A_DQS_sw_config_MASK (0x6000000U) macro
50233 …int32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DQS_sw_config_SHIFT)) & IOMUXD_QSPI1A_DQS_sw_config_MASK)
DMIMX8QM6_dsp.h53063 #define IOMUXD_QSPI1A_DQS_sw_config_MASK (0x6000000U) macro
53071 …int32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DQS_sw_config_SHIFT)) & IOMUXD_QSPI1A_DQS_sw_config_MASK)
DMIMX8QM6_cm4_core1.h38141 #define IOMUXD_QSPI1A_DQS_sw_config_MASK (0x6000000U) macro
38149 …int32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DQS_sw_config_SHIFT)) & IOMUXD_QSPI1A_DQS_sw_config_MASK)
DMIMX8QM6_cm4_core0.h38141 #define IOMUXD_QSPI1A_DQS_sw_config_MASK (0x6000000U) macro
38149 …int32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_DQS_sw_config_SHIFT)) & IOMUXD_QSPI1A_DQS_sw_config_MASK)