Home
last modified time | relevance | path

Searched refs:IOMUXC_SNVS_GPR_GPR32_LOCK_MASK (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm4.h50431 #define IOMUXC_SNVS_GPR_GPR32_LOCK_MASK (0xFFFF0000U) macro
50434 …(uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK)
DMIMXRT1165_cm7.h50434 #define IOMUXC_SNVS_GPR_GPR32_LOCK_MASK (0xFFFF0000U) macro
50437 …(uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h50964 #define IOMUXC_SNVS_GPR_GPR32_LOCK_MASK (0xFFFF0000U) macro
50967 …(uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h50961 #define IOMUXC_SNVS_GPR_GPR32_LOCK_MASK (0xFFFF0000U) macro
50964 …(uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK)
DMIMXRT1175_cm7.h50964 #define IOMUXC_SNVS_GPR_GPR32_LOCK_MASK (0xFFFF0000U) macro
50967 …(uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm7.h52966 #define IOMUXC_SNVS_GPR_GPR32_LOCK_MASK (0xFFFF0000U) macro
52969 …(uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK)
DMIMXRT1173_cm4.h52963 #define IOMUXC_SNVS_GPR_GPR32_LOCK_MASK (0xFFFF0000U) macro
52966 …(uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm7.h52439 #define IOMUXC_SNVS_GPR_GPR32_LOCK_MASK (0xFFFF0000U) macro
52442 …(uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK)
DMIMXRT1166_cm4.h52436 #define IOMUXC_SNVS_GPR_GPR32_LOCK_MASK (0xFFFF0000U) macro
52439 …(uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h52969 #define IOMUXC_SNVS_GPR_GPR32_LOCK_MASK (0xFFFF0000U) macro
52972 …(uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h63636 #define IOMUXC_SNVS_GPR_GPR32_LOCK_MASK (0xFFFF0000U) macro
63639 …(uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK)
DMIMXRT1176_cm4.h63633 #define IOMUXC_SNVS_GPR_GPR32_LOCK_MASK (0xFFFF0000U) macro
63636 …(uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK)