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Searched refs:IOMUXC_LPSR_GPR (Results 1 – 20 of 20) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/drivers/iee_apc/
Dfsl_iee_apc.c36 IOMUXC_LPSR_GPR->GPR25 |= IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK; in IEE_APC_GlobalEnable()
58 IOMUXC_LPSR_GPR->GPR25 &= ~IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK; in IEE_APC_GlobalDisable()
99 IOMUXC_LPSR_GPR->GPR2 |= startAddr & IOMUXC_LPSR_GPR_APC_ADDR_MASK; in IEE_APC_SetRegionConfig()
100 IOMUXC_LPSR_GPR->GPR3 |= endAddr & IOMUXC_LPSR_GPR_APC_ADDR_MASK; in IEE_APC_SetRegionConfig()
112 IOMUXC_LPSR_GPR->GPR4 |= startAddr & IOMUXC_LPSR_GPR_APC_ADDR_MASK; in IEE_APC_SetRegionConfig()
113 IOMUXC_LPSR_GPR->GPR5 |= endAddr & IOMUXC_LPSR_GPR_APC_ADDR_MASK; in IEE_APC_SetRegionConfig()
124 IOMUXC_LPSR_GPR->GPR6 |= startAddr & IOMUXC_LPSR_GPR_APC_ADDR_MASK; in IEE_APC_SetRegionConfig()
125 IOMUXC_LPSR_GPR->GPR7 |= endAddr & IOMUXC_LPSR_GPR_APC_ADDR_MASK; in IEE_APC_SetRegionConfig()
136 IOMUXC_LPSR_GPR->GPR8 |= startAddr & IOMUXC_LPSR_GPR_APC_ADDR_MASK; in IEE_APC_SetRegionConfig()
137 IOMUXC_LPSR_GPR->GPR9 |= endAddr & IOMUXC_LPSR_GPR_APC_ADDR_MASK; in IEE_APC_SetRegionConfig()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/mcuxpresso/
Dboot_multicore_slave.c49 IOMUXC_LPSR_GPR->GPR0 = IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW(bootAddress >> 3u); in boot_multicore_slave()
50 IOMUXC_LPSR_GPR->GPR1 = IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH(bootAddress >> 16u); in boot_multicore_slave()
65 IOMUXC_LPSR_GPR->GPR26 &= ~IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK; in boot_multicore_slave()
66 IOMUXC_LPSR_GPR->GPR26 |= IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR(bootAddress >> 7u); in boot_multicore_slave()
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1175/
Dfsl_pm_device.c1381 IOMUXC_LPSR_GPR->GPR26 &= ~IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK; in PM_DEV_PreparePowerSetting()
1382 IOMUXC_LPSR_GPR->GPR26 |= IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR(PM_DEV_VECTOR_TABLE >> 7); in PM_DEV_PreparePowerSetting()
1395 IOMUXC_LPSR_GPR->GPR34 |= IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK; in PM_DEV_PreparePowerSetting()
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1171/
Dfsl_pm_device.c1381 IOMUXC_LPSR_GPR->GPR26 &= ~IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK; in PM_DEV_PreparePowerSetting()
1382 IOMUXC_LPSR_GPR->GPR26 |= IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR(PM_DEV_VECTOR_TABLE >> 7); in PM_DEV_PreparePowerSetting()
1395 IOMUXC_LPSR_GPR->GPR34 |= IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK; in PM_DEV_PreparePowerSetting()
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1172/
Dfsl_pm_device.c1381 IOMUXC_LPSR_GPR->GPR26 &= ~IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK; in PM_DEV_PreparePowerSetting()
1382 IOMUXC_LPSR_GPR->GPR26 |= IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR(PM_DEV_VECTOR_TABLE >> 7); in PM_DEV_PreparePowerSetting()
1395 IOMUXC_LPSR_GPR->GPR34 |= IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK; in PM_DEV_PreparePowerSetting()
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1176/
Dfsl_pm_device.c1381 IOMUXC_LPSR_GPR->GPR26 &= ~IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK; in PM_DEV_PreparePowerSetting()
1382 IOMUXC_LPSR_GPR->GPR26 |= IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR(PM_DEV_VECTOR_TABLE >> 7); in PM_DEV_PreparePowerSetting()
1395 IOMUXC_LPSR_GPR->GPR34 |= IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK; in PM_DEV_PreparePowerSetting()
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1173/
Dfsl_pm_device.c1381 IOMUXC_LPSR_GPR->GPR26 &= ~IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK; in PM_DEV_PreparePowerSetting()
1382 IOMUXC_LPSR_GPR->GPR26 |= IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR(PM_DEV_VECTOR_TABLE >> 7); in PM_DEV_PreparePowerSetting()
1395 IOMUXC_LPSR_GPR->GPR34 |= IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK; in PM_DEV_PreparePowerSetting()
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h27864 #define IOMUXC_LPSR_GPR ((IOMUXC_LPSR_GPR_Type *)IOMUXC_LPSR_GPR_BASE) macro
27865 #define IOMUXC_LPSR_GPR_BASE_PTR (IOMUXC_LPSR_GPR)
27869 #define IOMUXC_LPSR_GPR_BASE_PTRS { IOMUXC_LPSR_GPR }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h49825 #define IOMUXC_LPSR_GPR ((IOMUXC_LPSR_GPR_Type *)IOMUXC_LPSR_GPR_BASE) macro
49829 #define IOMUXC_LPSR_GPR_BASE_PTRS { IOMUXC_LPSR_GPR }
DMIMXRT1175_cm7.h49828 #define IOMUXC_LPSR_GPR ((IOMUXC_LPSR_GPR_Type *)IOMUXC_LPSR_GPR_BASE) macro
49832 #define IOMUXC_LPSR_GPR_BASE_PTRS { IOMUXC_LPSR_GPR }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h49298 #define IOMUXC_LPSR_GPR ((IOMUXC_LPSR_GPR_Type *)IOMUXC_LPSR_GPR_BASE) macro
49302 #define IOMUXC_LPSR_GPR_BASE_PTRS { IOMUXC_LPSR_GPR }
DMIMXRT1165_cm4.h49295 #define IOMUXC_LPSR_GPR ((IOMUXC_LPSR_GPR_Type *)IOMUXC_LPSR_GPR_BASE) macro
49299 #define IOMUXC_LPSR_GPR_BASE_PTRS { IOMUXC_LPSR_GPR }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h49828 #define IOMUXC_LPSR_GPR ((IOMUXC_LPSR_GPR_Type *)IOMUXC_LPSR_GPR_BASE) macro
49832 #define IOMUXC_LPSR_GPR_BASE_PTRS { IOMUXC_LPSR_GPR }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h51300 #define IOMUXC_LPSR_GPR ((IOMUXC_LPSR_GPR_Type *)IOMUXC_LPSR_GPR_BASE) macro
51304 #define IOMUXC_LPSR_GPR_BASE_PTRS { IOMUXC_LPSR_GPR }
DMIMXRT1166_cm7.h51303 #define IOMUXC_LPSR_GPR ((IOMUXC_LPSR_GPR_Type *)IOMUXC_LPSR_GPR_BASE) macro
51307 #define IOMUXC_LPSR_GPR_BASE_PTRS { IOMUXC_LPSR_GPR }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h51827 #define IOMUXC_LPSR_GPR ((IOMUXC_LPSR_GPR_Type *)IOMUXC_LPSR_GPR_BASE) macro
51831 #define IOMUXC_LPSR_GPR_BASE_PTRS { IOMUXC_LPSR_GPR }
DMIMXRT1173_cm7.h51830 #define IOMUXC_LPSR_GPR ((IOMUXC_LPSR_GPR_Type *)IOMUXC_LPSR_GPR_BASE) macro
51834 #define IOMUXC_LPSR_GPR_BASE_PTRS { IOMUXC_LPSR_GPR }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h51833 #define IOMUXC_LPSR_GPR ((IOMUXC_LPSR_GPR_Type *)IOMUXC_LPSR_GPR_BASE) macro
51837 #define IOMUXC_LPSR_GPR_BASE_PTRS { IOMUXC_LPSR_GPR }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h62500 #define IOMUXC_LPSR_GPR ((IOMUXC_LPSR_GPR_Type *)IOMUXC_LPSR_GPR_BASE) macro
62504 #define IOMUXC_LPSR_GPR_BASE_PTRS { IOMUXC_LPSR_GPR }
DMIMXRT1176_cm4.h62497 #define IOMUXC_LPSR_GPR ((IOMUXC_LPSR_GPR_Type *)IOMUXC_LPSR_GPR_BASE) macro
62501 #define IOMUXC_LPSR_GPR_BASE_PTRS { IOMUXC_LPSR_GPR }