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Searched refs:IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h43897 #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK (0x7U) macro
43900 …t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK)
DMIMXRT1175_cm7.h43900 #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK (0x7U) macro
43903 …t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h43424 #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK (0x7U) macro
43427 …t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK)
DMIMXRT1165_cm4.h43421 #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK (0x7U) macro
43424 …t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h43900 #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK (0x7U) macro
43903 …t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h45426 #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK (0x7U) macro
45429 …t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK)
DMIMXRT1166_cm7.h45429 #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK (0x7U) macro
45432 …t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h45899 #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK (0x7U) macro
45902 …t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK)
DMIMXRT1173_cm7.h45902 #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK (0x7U) macro
45905 …t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h45905 #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK (0x7U) macro
45908 …t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h56572 #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK (0x7U) macro
56575 …t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK)
DMIMXRT1176_cm4.h56569 #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK (0x7U) macro
56572 …t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK)