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Searched refs:INT_MASK (Results 1 – 25 of 65) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/smartcard/
Dfsl_smartcard_emvsim.c82 base->INT_MASK |= (EMVSIM_INT_MASK_ETC_IM_MASK | EMVSIM_INT_MASK_TDT_IM_MASK); in smartcard_emvsim_CompleteSendData()
113 base->INT_MASK |= (EMVSIM_INT_MASK_RDT_IM_MASK | EMVSIM_INT_MASK_RX_DATA_IM_MASK); in smartcard_emvsim_CompleteReceiveData()
156 base->INT_MASK |= EMVSIM_INT_MASK_GPCNT1_IM_MASK; in smartcard_emvsim_StartSendData()
187 base->INT_MASK &= ~EMVSIM_INT_MASK_TDT_IM_MASK; in smartcard_emvsim_StartSendData()
203 base->INT_MASK &= ~EMVSIM_INT_MASK_BWT_ERR_IM_MASK; in smartcard_emvsim_StartReceiveData()
224 base->INT_MASK &= ~EMVSIM_INT_MASK_RDT_IM_MASK; in smartcard_emvsim_StartReceiveData()
230 base->INT_MASK &= ~EMVSIM_INT_MASK_RX_DATA_IM_MASK; in smartcard_emvsim_StartReceiveData()
284 base->INT_MASK &= ~EMVSIM_INT_MASK_TNACK_IM_MASK; in smartcard_emvsim_SetTransferType()
315 base->INT_MASK &= ~EMVSIM_INT_MASK_TNACK_IM_MASK; in smartcard_emvsim_SetTransferType()
437 base->INT_MASK = 0x7FFFu; in SMARTCARD_EMVSIM_Init()
[all …]
Dfsl_smartcard_phy_emvsim.c155 emvsimBase->INT_MASK &= ~EMVSIM_INT_MASK_GPCNT0_IM_MASK; in SMARTCARD_PHY_Activate()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h4177 __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */ member
16981 __IO uint32_t INT_MASK; /**< TRNG Mask Register, offset: 0xA8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h4177 __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */ member
16981 __IO uint32_t INT_MASK; /**< TRNG Mask Register, offset: 0xA8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW20Z4/
DMKW20Z4.h8219 __IO uint32_t INT_MASK; /**< RNG Mask Register, offset: 0xB8 */ member
8275 #define TRNG_INT_MASK_REG(base) ((base)->INT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW30Z4/
DMKW30Z4.h8219 __IO uint32_t INT_MASK; /**< RNG Mask Register, offset: 0xB8 */ member
8275 #define TRNG_INT_MASK_REG(base) ((base)->INT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/
DK32L3A60_cm4.h5281 __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */ member
21195 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ member
DK32L3A60_cm0plus.h4334 __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */ member
21305 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW40Z4/
DMKW40Z4.h8219 __IO uint32_t INT_MASK; /**< RNG Mask Register, offset: 0xB8 */ member
8275 #define TRNG_INT_MASK_REG(base) ((base)->INT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h8744 __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */ member
24179 __IO uint32_t INT_MASK; /**< RNG Mask Register, offset: 0xB8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h8738 __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */ member
25159 __IO uint32_t INT_MASK; /**< RNG Mask Register, offset: 0xB8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW31Z4/
DMKW31Z4.h7306 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xB8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW21Z4/
DMKW21Z4.h7235 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xB8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW41Z4/
DMKW41Z4.h7306 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xB8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV56F24/
DMKV56F24.h25262 __IO uint32_t INT_MASK; /**< RNG Mask Register, offset: 0xB8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV58F24/
DMKV58F24.h27028 __IO uint32_t INT_MASK; /**< RNG Mask Register, offset: 0xB8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h27701 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ member
DMIMXRT685S_cm33.h37352 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h23813 __IO uint32_t INT_MASK; /**< RNG Mask Register, offset: 0xA8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h23815 __IO uint32_t INT_MASK; /**< RNG Mask Register, offset: 0xA8 */ member
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h17260 …__IO uint32_t INT_MASK; /**< SIM Interrupt Mask Register, offset: 0… member
17302 #define SIM_INT_MASK_REG(base) ((base)->INT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h34261 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h34262 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h32125 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h29182 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ member

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