/hal_nxp-latest/mcux/mcux-sdk/drivers/smartcard/ |
D | fsl_smartcard_emvsim.c | 82 base->INT_MASK |= (EMVSIM_INT_MASK_ETC_IM_MASK | EMVSIM_INT_MASK_TDT_IM_MASK); in smartcard_emvsim_CompleteSendData() 113 base->INT_MASK |= (EMVSIM_INT_MASK_RDT_IM_MASK | EMVSIM_INT_MASK_RX_DATA_IM_MASK); in smartcard_emvsim_CompleteReceiveData() 156 base->INT_MASK |= EMVSIM_INT_MASK_GPCNT1_IM_MASK; in smartcard_emvsim_StartSendData() 187 base->INT_MASK &= ~EMVSIM_INT_MASK_TDT_IM_MASK; in smartcard_emvsim_StartSendData() 203 base->INT_MASK &= ~EMVSIM_INT_MASK_BWT_ERR_IM_MASK; in smartcard_emvsim_StartReceiveData() 224 base->INT_MASK &= ~EMVSIM_INT_MASK_RDT_IM_MASK; in smartcard_emvsim_StartReceiveData() 230 base->INT_MASK &= ~EMVSIM_INT_MASK_RX_DATA_IM_MASK; in smartcard_emvsim_StartReceiveData() 284 base->INT_MASK &= ~EMVSIM_INT_MASK_TNACK_IM_MASK; in smartcard_emvsim_SetTransferType() 315 base->INT_MASK &= ~EMVSIM_INT_MASK_TNACK_IM_MASK; in smartcard_emvsim_SetTransferType() 437 base->INT_MASK = 0x7FFFu; in SMARTCARD_EMVSIM_Init() [all …]
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D | fsl_smartcard_phy_emvsim.c | 155 emvsimBase->INT_MASK &= ~EMVSIM_INT_MASK_GPCNT0_IM_MASK; in SMARTCARD_PHY_Activate()
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/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/ |
D | K32L2A31A.h | 4177 __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */ member 16981 __IO uint32_t INT_MASK; /**< TRNG Mask Register, offset: 0xA8 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/ |
D | K32L2A41A.h | 4177 __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */ member 16981 __IO uint32_t INT_MASK; /**< TRNG Mask Register, offset: 0xA8 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MKW20Z4/ |
D | MKW20Z4.h | 8219 __IO uint32_t INT_MASK; /**< RNG Mask Register, offset: 0xB8 */ member 8275 #define TRNG_INT_MASK_REG(base) ((base)->INT_MASK)
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/hal_nxp-latest/mcux/mcux-sdk/devices/MKW30Z4/ |
D | MKW30Z4.h | 8219 __IO uint32_t INT_MASK; /**< RNG Mask Register, offset: 0xB8 */ member 8275 #define TRNG_INT_MASK_REG(base) ((base)->INT_MASK)
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/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/ |
D | K32L3A60_cm4.h | 5281 __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */ member 21195 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ member
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D | K32L3A60_cm0plus.h | 4334 __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */ member 21305 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MKW40Z4/ |
D | MKW40Z4.h | 8219 __IO uint32_t INT_MASK; /**< RNG Mask Register, offset: 0xB8 */ member 8275 #define TRNG_INT_MASK_REG(base) ((base)->INT_MASK)
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/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/ |
D | MK80F25615.h | 8744 __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */ member 24179 __IO uint32_t INT_MASK; /**< RNG Mask Register, offset: 0xB8 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/ |
D | MK82F25615.h | 8738 __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */ member 25159 __IO uint32_t INT_MASK; /**< RNG Mask Register, offset: 0xB8 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MKW31Z4/ |
D | MKW31Z4.h | 7306 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xB8 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MKW21Z4/ |
D | MKW21Z4.h | 7235 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xB8 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MKW41Z4/ |
D | MKW41Z4.h | 7306 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xB8 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MKV56F24/ |
D | MKV56F24.h | 25262 __IO uint32_t INT_MASK; /**< RNG Mask Register, offset: 0xB8 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MKV58F24/ |
D | MKV58F24.h | 27028 __IO uint32_t INT_MASK; /**< RNG Mask Register, offset: 0xB8 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/ |
D | MIMXRT685S_dsp.h | 27701 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ member
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D | MIMXRT685S_cm33.h | 37352 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/ |
D | MK27FA15.h | 23813 __IO uint32_t INT_MASK; /**< RNG Mask Register, offset: 0xA8 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/ |
D | MK28FA15.h | 23815 __IO uint32_t INT_MASK; /**< RNG Mask Register, offset: 0xA8 */ member
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/hal_nxp-latest/imx/devices/MCIMX7D/ |
D | MCIMX7D_M4.h | 17260 …__IO uint32_t INT_MASK; /**< SIM Interrupt Mask Register, offset: 0… member 17302 #define SIM_INT_MASK_REG(base) ((base)->INT_MASK)
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/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/ |
D | MCIMX7U3_cm4.h | 34261 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/ |
D | MCIMX7U5_cm4.h | 34262 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/ |
D | MIMXRT1015.h | 32125 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/ |
D | MIMXRT1011.h | 29182 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ member
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