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Searched refs:INT_ENABLE_D0 (Results 1 – 11 of 11) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/drivers/lcdifv3/
Dfsl_lcdifv3.h296 base->INT_ENABLE_D0 |= mask; in LCDIFV3_EnableInterrupts()
309 base->INT_ENABLE_D0 &= ~mask; in LCDIFV3_DisableInterrupts()
Dfsl_lcdifv3.c76 base->INT_ENABLE_D0 = 0U; in LCDIFV3_ResetRegister()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML6/
DMIMX8ML6_cm7.h63197 …__IO uint32_t INT_ENABLE_D0; /**< Interrupt Enable Register for domain 0, offs… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML4/
DMIMX8ML4_cm7.h63197 …__IO uint32_t INT_ENABLE_D0; /**< Interrupt Enable Register for domain 0, offs… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML3/
DMIMX8ML3_cm7.h63197 …__IO uint32_t INT_ENABLE_D0; /**< Interrupt Enable Register for domain 0, offs… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9131/
DMIMX9131.h39226 …__IO uint32_t INT_ENABLE_D0; /**< Interrupt Enable Register for domain 0, offs… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML8/
DMIMX8ML8_dsp.h60498 …__IO uint32_t INT_ENABLE_D0; /**< Interrupt Enable Register for domain 0, offs… member
DMIMX8ML8_cm7.h63197 …__IO uint32_t INT_ENABLE_D0; /**< Interrupt Enable Register for domain 0, offs… member
DMIMX8ML8_ca53.h63217 …__IO uint32_t INT_ENABLE_D0; /**< Interrupt Enable Register for domain 0, offs… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/
DMIMX9352_cm33.h37965 …__IO uint32_t INT_ENABLE_D0; /**< Interrupt Enable Register for domain 0, offs… member
DMIMX9352_ca55.h40849 …__IO uint32_t INT_ENABLE_D0; /**< Interrupt Enable Register for domain 0, offs… member