1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_INTERRUPT_CONTROL.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_INTERRUPT_CONTROL 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_INTERRUPT_CONTROL_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_INTERRUPT_CONTROL_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- INTERRUPT_CONTROL Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup INTERRUPT_CONTROL_Peripheral_Access_Layer INTERRUPT_CONTROL Peripheral Access Layer 68 * @{ 69 */ 70 71 /** INTERRUPT_CONTROL - Size of Registers Arrays */ 72 #define INTERRUPT_CONTROL_ISRX_COUNT 1u 73 #define INTERRUPT_CONTROL_ICRX_COUNT 1u 74 #define INTERRUPT_CONTROL_IGRX_COUNT 1u 75 #define INTERRUPT_CONTROL_IVAX_COUNT 6u 76 #define INTERRUPT_CONTROL_ICFGX_COUNT 23u 77 78 /** INTERRUPT_CONTROL - Register Layout Typedef */ 79 typedef struct { 80 __I uint32_t ISRX[INTERRUPT_CONTROL_ISRX_COUNT]; /**< Interrupt Status Register, array offset: 0x0, array step: 0x4 */ 81 uint8_t RESERVED_0[28]; 82 __IO uint32_t ICRX[INTERRUPT_CONTROL_ICRX_COUNT]; /**< Interrupt Clear Register, array offset: 0x20, array step: 0x4 */ 83 uint8_t RESERVED_1[28]; 84 __IO uint32_t IGRX[INTERRUPT_CONTROL_IGRX_COUNT]; /**< Interrupt Generation Register, array offset: 0x40, array step: 0x4 */ 85 uint8_t RESERVED_2[28]; 86 __IO uint32_t IMR0; /**< Interrupt Mask Register, offset: 0x60 */ 87 uint8_t RESERVED_3[124]; 88 __IO uint32_t IGMR; /**< IGM Register, offset: 0xE0 */ 89 uint8_t RESERVED_4[36]; 90 __IO uint32_t IVAX[INTERRUPT_CONTROL_IVAX_COUNT]; /**< Interrupt Vector Address, array offset: 0x108, array step: 0x4 */ 91 uint8_t RESERVED_5[224]; 92 __IO uint32_t ICFG0; /**< ICFG0 Register, offset: 0x200 */ 93 __IO uint32_t ICFG1; /**< ICFG1 Register, offset: 0x204 */ 94 __IO uint32_t ICFG2; /**< ICFG2 Register, offset: 0x208 */ 95 __IO uint32_t ICFG3; /**< ICFG3 Register, offset: 0x20C */ 96 __IO uint32_t ICFG4; /**< ICFG4 Register, offset: 0x210 */ 97 __IO uint32_t ICFG5; /**< ICFG5 Register, offset: 0x214 */ 98 __IO uint32_t ICFG6; /**< ICFG6 Register, offset: 0x218 */ 99 uint8_t RESERVED_6[4]; 100 __IO uint32_t ICFG8; /**< ICFG8 Register, offset: 0x220 */ 101 __IO uint32_t ICFGX[INTERRUPT_CONTROL_ICFGX_COUNT]; /**< ICFGx Register, array offset: 0x224, array step: 0x4 */ 102 } INTERRUPT_CONTROL_Type, *INTERRUPT_CONTROL_MemMapPtr; 103 104 /** Number of instances of the INTERRUPT_CONTROL module. */ 105 #define INTERRUPT_CONTROL_INSTANCE_COUNT (1u) 106 107 /* INTERRUPT_CONTROL - Peripheral instance base addresses */ 108 /** Peripheral CEVA_SPF2__INTERRUPT_CONTROL base address */ 109 #define IP_CEVA_SPF2__INTERRUPT_CONTROL_BASE (0x24402100u) 110 /** Peripheral CEVA_SPF2__INTERRUPT_CONTROL base pointer */ 111 #define IP_CEVA_SPF2__INTERRUPT_CONTROL ((INTERRUPT_CONTROL_Type *)IP_CEVA_SPF2__INTERRUPT_CONTROL_BASE) 112 /** Array initializer of INTERRUPT_CONTROL peripheral base addresses */ 113 #define IP_INTERRUPT_CONTROL_BASE_ADDRS { IP_CEVA_SPF2__INTERRUPT_CONTROL_BASE } 114 /** Array initializer of INTERRUPT_CONTROL peripheral base pointers */ 115 #define IP_INTERRUPT_CONTROL_BASE_PTRS { IP_CEVA_SPF2__INTERRUPT_CONTROL } 116 117 /* ---------------------------------------------------------------------------- 118 -- INTERRUPT_CONTROL Register Masks 119 ---------------------------------------------------------------------------- */ 120 121 /*! 122 * @addtogroup INTERRUPT_CONTROL_Register_Masks INTERRUPT_CONTROL Register Masks 123 * @{ 124 */ 125 126 /*! @name ISRX - Interrupt Status Register */ 127 /*! @{ */ 128 129 #define INTERRUPT_CONTROL_ISRX_ISR_MASK (0xFFFFFFFFU) 130 #define INTERRUPT_CONTROL_ISRX_ISR_SHIFT (0U) 131 #define INTERRUPT_CONTROL_ISRX_ISR_WIDTH (32U) 132 #define INTERRUPT_CONTROL_ISRX_ISR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ISRX_ISR_SHIFT)) & INTERRUPT_CONTROL_ISRX_ISR_MASK) 133 /*! @} */ 134 135 /*! @name ICRX - Interrupt Clear Register */ 136 /*! @{ */ 137 138 #define INTERRUPT_CONTROL_ICRX_ICR_MASK (0xFFFFFFFFU) 139 #define INTERRUPT_CONTROL_ICRX_ICR_SHIFT (0U) 140 #define INTERRUPT_CONTROL_ICRX_ICR_WIDTH (32U) 141 #define INTERRUPT_CONTROL_ICRX_ICR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICRX_ICR_SHIFT)) & INTERRUPT_CONTROL_ICRX_ICR_MASK) 142 /*! @} */ 143 144 /*! @name IGRX - Interrupt Generation Register */ 145 /*! @{ */ 146 147 #define INTERRUPT_CONTROL_IGRX_IGR_MASK (0xFFFFFFFFU) 148 #define INTERRUPT_CONTROL_IGRX_IGR_SHIFT (0U) 149 #define INTERRUPT_CONTROL_IGRX_IGR_WIDTH (32U) 150 #define INTERRUPT_CONTROL_IGRX_IGR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_IGRX_IGR_SHIFT)) & INTERRUPT_CONTROL_IGRX_IGR_MASK) 151 /*! @} */ 152 153 /*! @name IMR0 - Interrupt Mask Register */ 154 /*! @{ */ 155 156 #define INTERRUPT_CONTROL_IMR0_IMR_0_MASK (0x1U) 157 #define INTERRUPT_CONTROL_IMR0_IMR_0_SHIFT (0U) 158 #define INTERRUPT_CONTROL_IMR0_IMR_0_WIDTH (1U) 159 #define INTERRUPT_CONTROL_IMR0_IMR_0(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_IMR0_IMR_0_SHIFT)) & INTERRUPT_CONTROL_IMR0_IMR_0_MASK) 160 161 #define INTERRUPT_CONTROL_IMR0_IMR0L_MASK (0x1EU) 162 #define INTERRUPT_CONTROL_IMR0_IMR0L_SHIFT (1U) 163 #define INTERRUPT_CONTROL_IMR0_IMR0L_WIDTH (4U) 164 #define INTERRUPT_CONTROL_IMR0_IMR0L(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_IMR0_IMR0L_SHIFT)) & INTERRUPT_CONTROL_IMR0_IMR0L_MASK) 165 166 #define INTERRUPT_CONTROL_IMR0_IMR0_5_MASK (0x20U) 167 #define INTERRUPT_CONTROL_IMR0_IMR0_5_SHIFT (5U) 168 #define INTERRUPT_CONTROL_IMR0_IMR0_5_WIDTH (1U) 169 #define INTERRUPT_CONTROL_IMR0_IMR0_5(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_IMR0_IMR0_5_SHIFT)) & INTERRUPT_CONTROL_IMR0_IMR0_5_MASK) 170 171 #define INTERRUPT_CONTROL_IMR0_IMR0H_MASK (0xFFFFFFC0U) 172 #define INTERRUPT_CONTROL_IMR0_IMR0H_SHIFT (6U) 173 #define INTERRUPT_CONTROL_IMR0_IMR0H_WIDTH (26U) 174 #define INTERRUPT_CONTROL_IMR0_IMR0H(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_IMR0_IMR0H_SHIFT)) & INTERRUPT_CONTROL_IMR0_IMR0H_MASK) 175 /*! @} */ 176 177 /*! @name IGMR - IGM Register */ 178 /*! @{ */ 179 180 #define INTERRUPT_CONTROL_IGMR_GM0_MASK (0x1U) 181 #define INTERRUPT_CONTROL_IGMR_GM0_SHIFT (0U) 182 #define INTERRUPT_CONTROL_IGMR_GM0_WIDTH (1U) 183 #define INTERRUPT_CONTROL_IGMR_GM0(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_IGMR_GM0_SHIFT)) & INTERRUPT_CONTROL_IGMR_GM0_MASK) 184 185 #define INTERRUPT_CONTROL_IGMR_CIL_MASK (0x10000U) 186 #define INTERRUPT_CONTROL_IGMR_CIL_SHIFT (16U) 187 #define INTERRUPT_CONTROL_IGMR_CIL_WIDTH (1U) 188 #define INTERRUPT_CONTROL_IGMR_CIL(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_IGMR_CIL_SHIFT)) & INTERRUPT_CONTROL_IGMR_CIL_MASK) 189 190 #define INTERRUPT_CONTROL_IGMR_CILP_MASK (0x20000U) 191 #define INTERRUPT_CONTROL_IGMR_CILP_SHIFT (17U) 192 #define INTERRUPT_CONTROL_IGMR_CILP_WIDTH (1U) 193 #define INTERRUPT_CONTROL_IGMR_CILP(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_IGMR_CILP_SHIFT)) & INTERRUPT_CONTROL_IGMR_CILP_MASK) 194 195 #define INTERRUPT_CONTROL_IGMR_ICUE_MASK (0x80000000U) 196 #define INTERRUPT_CONTROL_IGMR_ICUE_SHIFT (31U) 197 #define INTERRUPT_CONTROL_IGMR_ICUE_WIDTH (1U) 198 #define INTERRUPT_CONTROL_IGMR_ICUE(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_IGMR_ICUE_SHIFT)) & INTERRUPT_CONTROL_IGMR_ICUE_MASK) 199 /*! @} */ 200 201 /*! @name IVAX - Interrupt Vector Address */ 202 /*! @{ */ 203 204 #define INTERRUPT_CONTROL_IVAX_IVAX_MASK (0xFFFFFF00U) 205 #define INTERRUPT_CONTROL_IVAX_IVAX_SHIFT (8U) 206 #define INTERRUPT_CONTROL_IVAX_IVAX_WIDTH (24U) 207 #define INTERRUPT_CONTROL_IVAX_IVAX(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_IVAX_IVAX_SHIFT)) & INTERRUPT_CONTROL_IVAX_IVAX_MASK) 208 /*! @} */ 209 210 /*! @name ICFG0 - ICFG0 Register */ 211 /*! @{ */ 212 213 #define INTERRUPT_CONTROL_ICFG0_ISR_MASK (0x1U) 214 #define INTERRUPT_CONTROL_ICFG0_ISR_SHIFT (0U) 215 #define INTERRUPT_CONTROL_ICFG0_ISR_WIDTH (1U) 216 #define INTERRUPT_CONTROL_ICFG0_ISR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG0_ISR_SHIFT)) & INTERRUPT_CONTROL_ICFG0_ISR_MASK) 217 218 #define INTERRUPT_CONTROL_ICFG0_IMR_MASK (0x2U) 219 #define INTERRUPT_CONTROL_ICFG0_IMR_SHIFT (1U) 220 #define INTERRUPT_CONTROL_ICFG0_IMR_WIDTH (1U) 221 #define INTERRUPT_CONTROL_ICFG0_IMR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG0_IMR_SHIFT)) & INTERRUPT_CONTROL_ICFG0_IMR_MASK) 222 223 #define INTERRUPT_CONTROL_ICFG0_IMOD_MASK (0xCU) 224 #define INTERRUPT_CONTROL_ICFG0_IMOD_SHIFT (2U) 225 #define INTERRUPT_CONTROL_ICFG0_IMOD_WIDTH (2U) 226 #define INTERRUPT_CONTROL_ICFG0_IMOD(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG0_IMOD_SHIFT)) & INTERRUPT_CONTROL_ICFG0_IMOD_MASK) 227 228 #define INTERRUPT_CONTROL_ICFG0_IVI_MASK (0x1C0U) 229 #define INTERRUPT_CONTROL_ICFG0_IVI_SHIFT (6U) 230 #define INTERRUPT_CONTROL_ICFG0_IVI_WIDTH (3U) 231 #define INTERRUPT_CONTROL_ICFG0_IVI(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG0_IVI_SHIFT)) & INTERRUPT_CONTROL_ICFG0_IVI_MASK) 232 233 #define INTERRUPT_CONTROL_ICFG0_IPR_MASK (0x7000U) 234 #define INTERRUPT_CONTROL_ICFG0_IPR_SHIFT (12U) 235 #define INTERRUPT_CONTROL_ICFG0_IPR_WIDTH (3U) 236 #define INTERRUPT_CONTROL_ICFG0_IPR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG0_IPR_SHIFT)) & INTERRUPT_CONTROL_ICFG0_IPR_MASK) 237 /*! @} */ 238 239 /*! @name ICFG1 - ICFG1 Register */ 240 /*! @{ */ 241 242 #define INTERRUPT_CONTROL_ICFG1_ISR_MASK (0x1U) 243 #define INTERRUPT_CONTROL_ICFG1_ISR_SHIFT (0U) 244 #define INTERRUPT_CONTROL_ICFG1_ISR_WIDTH (1U) 245 #define INTERRUPT_CONTROL_ICFG1_ISR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG1_ISR_SHIFT)) & INTERRUPT_CONTROL_ICFG1_ISR_MASK) 246 247 #define INTERRUPT_CONTROL_ICFG1_IMR_MASK (0x2U) 248 #define INTERRUPT_CONTROL_ICFG1_IMR_SHIFT (1U) 249 #define INTERRUPT_CONTROL_ICFG1_IMR_WIDTH (1U) 250 #define INTERRUPT_CONTROL_ICFG1_IMR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG1_IMR_SHIFT)) & INTERRUPT_CONTROL_ICFG1_IMR_MASK) 251 252 #define INTERRUPT_CONTROL_ICFG1_IMOD_MASK (0xCU) 253 #define INTERRUPT_CONTROL_ICFG1_IMOD_SHIFT (2U) 254 #define INTERRUPT_CONTROL_ICFG1_IMOD_WIDTH (2U) 255 #define INTERRUPT_CONTROL_ICFG1_IMOD(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG1_IMOD_SHIFT)) & INTERRUPT_CONTROL_ICFG1_IMOD_MASK) 256 257 #define INTERRUPT_CONTROL_ICFG1_IVI_MASK (0x1C0U) 258 #define INTERRUPT_CONTROL_ICFG1_IVI_SHIFT (6U) 259 #define INTERRUPT_CONTROL_ICFG1_IVI_WIDTH (3U) 260 #define INTERRUPT_CONTROL_ICFG1_IVI(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG1_IVI_SHIFT)) & INTERRUPT_CONTROL_ICFG1_IVI_MASK) 261 262 #define INTERRUPT_CONTROL_ICFG1_IPR_MASK (0x7000U) 263 #define INTERRUPT_CONTROL_ICFG1_IPR_SHIFT (12U) 264 #define INTERRUPT_CONTROL_ICFG1_IPR_WIDTH (3U) 265 #define INTERRUPT_CONTROL_ICFG1_IPR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG1_IPR_SHIFT)) & INTERRUPT_CONTROL_ICFG1_IPR_MASK) 266 /*! @} */ 267 268 /*! @name ICFG2 - ICFG2 Register */ 269 /*! @{ */ 270 271 #define INTERRUPT_CONTROL_ICFG2_ISR_MASK (0x1U) 272 #define INTERRUPT_CONTROL_ICFG2_ISR_SHIFT (0U) 273 #define INTERRUPT_CONTROL_ICFG2_ISR_WIDTH (1U) 274 #define INTERRUPT_CONTROL_ICFG2_ISR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG2_ISR_SHIFT)) & INTERRUPT_CONTROL_ICFG2_ISR_MASK) 275 276 #define INTERRUPT_CONTROL_ICFG2_IMR_MASK (0x2U) 277 #define INTERRUPT_CONTROL_ICFG2_IMR_SHIFT (1U) 278 #define INTERRUPT_CONTROL_ICFG2_IMR_WIDTH (1U) 279 #define INTERRUPT_CONTROL_ICFG2_IMR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG2_IMR_SHIFT)) & INTERRUPT_CONTROL_ICFG2_IMR_MASK) 280 281 #define INTERRUPT_CONTROL_ICFG2_IMOD_MASK (0xCU) 282 #define INTERRUPT_CONTROL_ICFG2_IMOD_SHIFT (2U) 283 #define INTERRUPT_CONTROL_ICFG2_IMOD_WIDTH (2U) 284 #define INTERRUPT_CONTROL_ICFG2_IMOD(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG2_IMOD_SHIFT)) & INTERRUPT_CONTROL_ICFG2_IMOD_MASK) 285 286 #define INTERRUPT_CONTROL_ICFG2_IVI_MASK (0x1C0U) 287 #define INTERRUPT_CONTROL_ICFG2_IVI_SHIFT (6U) 288 #define INTERRUPT_CONTROL_ICFG2_IVI_WIDTH (3U) 289 #define INTERRUPT_CONTROL_ICFG2_IVI(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG2_IVI_SHIFT)) & INTERRUPT_CONTROL_ICFG2_IVI_MASK) 290 291 #define INTERRUPT_CONTROL_ICFG2_IPR_MASK (0x7000U) 292 #define INTERRUPT_CONTROL_ICFG2_IPR_SHIFT (12U) 293 #define INTERRUPT_CONTROL_ICFG2_IPR_WIDTH (3U) 294 #define INTERRUPT_CONTROL_ICFG2_IPR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG2_IPR_SHIFT)) & INTERRUPT_CONTROL_ICFG2_IPR_MASK) 295 /*! @} */ 296 297 /*! @name ICFG3 - ICFG3 Register */ 298 /*! @{ */ 299 300 #define INTERRUPT_CONTROL_ICFG3_ISR_MASK (0x1U) 301 #define INTERRUPT_CONTROL_ICFG3_ISR_SHIFT (0U) 302 #define INTERRUPT_CONTROL_ICFG3_ISR_WIDTH (1U) 303 #define INTERRUPT_CONTROL_ICFG3_ISR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG3_ISR_SHIFT)) & INTERRUPT_CONTROL_ICFG3_ISR_MASK) 304 305 #define INTERRUPT_CONTROL_ICFG3_IMR_MASK (0x2U) 306 #define INTERRUPT_CONTROL_ICFG3_IMR_SHIFT (1U) 307 #define INTERRUPT_CONTROL_ICFG3_IMR_WIDTH (1U) 308 #define INTERRUPT_CONTROL_ICFG3_IMR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG3_IMR_SHIFT)) & INTERRUPT_CONTROL_ICFG3_IMR_MASK) 309 310 #define INTERRUPT_CONTROL_ICFG3_IMOD_MASK (0xCU) 311 #define INTERRUPT_CONTROL_ICFG3_IMOD_SHIFT (2U) 312 #define INTERRUPT_CONTROL_ICFG3_IMOD_WIDTH (2U) 313 #define INTERRUPT_CONTROL_ICFG3_IMOD(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG3_IMOD_SHIFT)) & INTERRUPT_CONTROL_ICFG3_IMOD_MASK) 314 315 #define INTERRUPT_CONTROL_ICFG3_IVI_MASK (0x1C0U) 316 #define INTERRUPT_CONTROL_ICFG3_IVI_SHIFT (6U) 317 #define INTERRUPT_CONTROL_ICFG3_IVI_WIDTH (3U) 318 #define INTERRUPT_CONTROL_ICFG3_IVI(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG3_IVI_SHIFT)) & INTERRUPT_CONTROL_ICFG3_IVI_MASK) 319 320 #define INTERRUPT_CONTROL_ICFG3_IPR_MASK (0x7000U) 321 #define INTERRUPT_CONTROL_ICFG3_IPR_SHIFT (12U) 322 #define INTERRUPT_CONTROL_ICFG3_IPR_WIDTH (3U) 323 #define INTERRUPT_CONTROL_ICFG3_IPR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG3_IPR_SHIFT)) & INTERRUPT_CONTROL_ICFG3_IPR_MASK) 324 /*! @} */ 325 326 /*! @name ICFG4 - ICFG4 Register */ 327 /*! @{ */ 328 329 #define INTERRUPT_CONTROL_ICFG4_ISR_MASK (0x1U) 330 #define INTERRUPT_CONTROL_ICFG4_ISR_SHIFT (0U) 331 #define INTERRUPT_CONTROL_ICFG4_ISR_WIDTH (1U) 332 #define INTERRUPT_CONTROL_ICFG4_ISR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG4_ISR_SHIFT)) & INTERRUPT_CONTROL_ICFG4_ISR_MASK) 333 334 #define INTERRUPT_CONTROL_ICFG4_IMR_MASK (0x2U) 335 #define INTERRUPT_CONTROL_ICFG4_IMR_SHIFT (1U) 336 #define INTERRUPT_CONTROL_ICFG4_IMR_WIDTH (1U) 337 #define INTERRUPT_CONTROL_ICFG4_IMR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG4_IMR_SHIFT)) & INTERRUPT_CONTROL_ICFG4_IMR_MASK) 338 339 #define INTERRUPT_CONTROL_ICFG4_IMOD_MASK (0xCU) 340 #define INTERRUPT_CONTROL_ICFG4_IMOD_SHIFT (2U) 341 #define INTERRUPT_CONTROL_ICFG4_IMOD_WIDTH (2U) 342 #define INTERRUPT_CONTROL_ICFG4_IMOD(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG4_IMOD_SHIFT)) & INTERRUPT_CONTROL_ICFG4_IMOD_MASK) 343 344 #define INTERRUPT_CONTROL_ICFG4_IVI_MASK (0x1C0U) 345 #define INTERRUPT_CONTROL_ICFG4_IVI_SHIFT (6U) 346 #define INTERRUPT_CONTROL_ICFG4_IVI_WIDTH (3U) 347 #define INTERRUPT_CONTROL_ICFG4_IVI(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG4_IVI_SHIFT)) & INTERRUPT_CONTROL_ICFG4_IVI_MASK) 348 349 #define INTERRUPT_CONTROL_ICFG4_IPR_MASK (0x7000U) 350 #define INTERRUPT_CONTROL_ICFG4_IPR_SHIFT (12U) 351 #define INTERRUPT_CONTROL_ICFG4_IPR_WIDTH (3U) 352 #define INTERRUPT_CONTROL_ICFG4_IPR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG4_IPR_SHIFT)) & INTERRUPT_CONTROL_ICFG4_IPR_MASK) 353 /*! @} */ 354 355 /*! @name ICFG5 - ICFG5 Register */ 356 /*! @{ */ 357 358 #define INTERRUPT_CONTROL_ICFG5_ISR_MASK (0x1U) 359 #define INTERRUPT_CONTROL_ICFG5_ISR_SHIFT (0U) 360 #define INTERRUPT_CONTROL_ICFG5_ISR_WIDTH (1U) 361 #define INTERRUPT_CONTROL_ICFG5_ISR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG5_ISR_SHIFT)) & INTERRUPT_CONTROL_ICFG5_ISR_MASK) 362 363 #define INTERRUPT_CONTROL_ICFG5_IMR_MASK (0x2U) 364 #define INTERRUPT_CONTROL_ICFG5_IMR_SHIFT (1U) 365 #define INTERRUPT_CONTROL_ICFG5_IMR_WIDTH (1U) 366 #define INTERRUPT_CONTROL_ICFG5_IMR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG5_IMR_SHIFT)) & INTERRUPT_CONTROL_ICFG5_IMR_MASK) 367 368 #define INTERRUPT_CONTROL_ICFG5_IMOD_MASK (0xCU) 369 #define INTERRUPT_CONTROL_ICFG5_IMOD_SHIFT (2U) 370 #define INTERRUPT_CONTROL_ICFG5_IMOD_WIDTH (2U) 371 #define INTERRUPT_CONTROL_ICFG5_IMOD(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG5_IMOD_SHIFT)) & INTERRUPT_CONTROL_ICFG5_IMOD_MASK) 372 373 #define INTERRUPT_CONTROL_ICFG5_IVI_MASK (0x1C0U) 374 #define INTERRUPT_CONTROL_ICFG5_IVI_SHIFT (6U) 375 #define INTERRUPT_CONTROL_ICFG5_IVI_WIDTH (3U) 376 #define INTERRUPT_CONTROL_ICFG5_IVI(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG5_IVI_SHIFT)) & INTERRUPT_CONTROL_ICFG5_IVI_MASK) 377 378 #define INTERRUPT_CONTROL_ICFG5_IPR_MASK (0x7000U) 379 #define INTERRUPT_CONTROL_ICFG5_IPR_SHIFT (12U) 380 #define INTERRUPT_CONTROL_ICFG5_IPR_WIDTH (3U) 381 #define INTERRUPT_CONTROL_ICFG5_IPR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG5_IPR_SHIFT)) & INTERRUPT_CONTROL_ICFG5_IPR_MASK) 382 /*! @} */ 383 384 /*! @name ICFG6 - ICFG6 Register */ 385 /*! @{ */ 386 387 #define INTERRUPT_CONTROL_ICFG6_ISR_MASK (0x1U) 388 #define INTERRUPT_CONTROL_ICFG6_ISR_SHIFT (0U) 389 #define INTERRUPT_CONTROL_ICFG6_ISR_WIDTH (1U) 390 #define INTERRUPT_CONTROL_ICFG6_ISR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG6_ISR_SHIFT)) & INTERRUPT_CONTROL_ICFG6_ISR_MASK) 391 392 #define INTERRUPT_CONTROL_ICFG6_IMR_MASK (0x2U) 393 #define INTERRUPT_CONTROL_ICFG6_IMR_SHIFT (1U) 394 #define INTERRUPT_CONTROL_ICFG6_IMR_WIDTH (1U) 395 #define INTERRUPT_CONTROL_ICFG6_IMR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG6_IMR_SHIFT)) & INTERRUPT_CONTROL_ICFG6_IMR_MASK) 396 397 #define INTERRUPT_CONTROL_ICFG6_IMOD_MASK (0xCU) 398 #define INTERRUPT_CONTROL_ICFG6_IMOD_SHIFT (2U) 399 #define INTERRUPT_CONTROL_ICFG6_IMOD_WIDTH (2U) 400 #define INTERRUPT_CONTROL_ICFG6_IMOD(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG6_IMOD_SHIFT)) & INTERRUPT_CONTROL_ICFG6_IMOD_MASK) 401 402 #define INTERRUPT_CONTROL_ICFG6_IVI_MASK (0x1C0U) 403 #define INTERRUPT_CONTROL_ICFG6_IVI_SHIFT (6U) 404 #define INTERRUPT_CONTROL_ICFG6_IVI_WIDTH (3U) 405 #define INTERRUPT_CONTROL_ICFG6_IVI(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG6_IVI_SHIFT)) & INTERRUPT_CONTROL_ICFG6_IVI_MASK) 406 407 #define INTERRUPT_CONTROL_ICFG6_IPR_MASK (0x7000U) 408 #define INTERRUPT_CONTROL_ICFG6_IPR_SHIFT (12U) 409 #define INTERRUPT_CONTROL_ICFG6_IPR_WIDTH (3U) 410 #define INTERRUPT_CONTROL_ICFG6_IPR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG6_IPR_SHIFT)) & INTERRUPT_CONTROL_ICFG6_IPR_MASK) 411 /*! @} */ 412 413 /*! @name ICFG8 - ICFG8 Register */ 414 /*! @{ */ 415 416 #define INTERRUPT_CONTROL_ICFG8_ISR_MASK (0x1U) 417 #define INTERRUPT_CONTROL_ICFG8_ISR_SHIFT (0U) 418 #define INTERRUPT_CONTROL_ICFG8_ISR_WIDTH (1U) 419 #define INTERRUPT_CONTROL_ICFG8_ISR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG8_ISR_SHIFT)) & INTERRUPT_CONTROL_ICFG8_ISR_MASK) 420 421 #define INTERRUPT_CONTROL_ICFG8_IMR_MASK (0x2U) 422 #define INTERRUPT_CONTROL_ICFG8_IMR_SHIFT (1U) 423 #define INTERRUPT_CONTROL_ICFG8_IMR_WIDTH (1U) 424 #define INTERRUPT_CONTROL_ICFG8_IMR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG8_IMR_SHIFT)) & INTERRUPT_CONTROL_ICFG8_IMR_MASK) 425 426 #define INTERRUPT_CONTROL_ICFG8_IMOD_MASK (0xCU) 427 #define INTERRUPT_CONTROL_ICFG8_IMOD_SHIFT (2U) 428 #define INTERRUPT_CONTROL_ICFG8_IMOD_WIDTH (2U) 429 #define INTERRUPT_CONTROL_ICFG8_IMOD(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG8_IMOD_SHIFT)) & INTERRUPT_CONTROL_ICFG8_IMOD_MASK) 430 431 #define INTERRUPT_CONTROL_ICFG8_IVI_MASK (0x1C0U) 432 #define INTERRUPT_CONTROL_ICFG8_IVI_SHIFT (6U) 433 #define INTERRUPT_CONTROL_ICFG8_IVI_WIDTH (3U) 434 #define INTERRUPT_CONTROL_ICFG8_IVI(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG8_IVI_SHIFT)) & INTERRUPT_CONTROL_ICFG8_IVI_MASK) 435 436 #define INTERRUPT_CONTROL_ICFG8_IPR_MASK (0x7000U) 437 #define INTERRUPT_CONTROL_ICFG8_IPR_SHIFT (12U) 438 #define INTERRUPT_CONTROL_ICFG8_IPR_WIDTH (3U) 439 #define INTERRUPT_CONTROL_ICFG8_IPR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFG8_IPR_SHIFT)) & INTERRUPT_CONTROL_ICFG8_IPR_MASK) 440 /*! @} */ 441 442 /*! @name ICFGX - ICFGx Register */ 443 /*! @{ */ 444 445 #define INTERRUPT_CONTROL_ICFGX_ISR_MASK (0x1U) 446 #define INTERRUPT_CONTROL_ICFGX_ISR_SHIFT (0U) 447 #define INTERRUPT_CONTROL_ICFGX_ISR_WIDTH (1U) 448 #define INTERRUPT_CONTROL_ICFGX_ISR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFGX_ISR_SHIFT)) & INTERRUPT_CONTROL_ICFGX_ISR_MASK) 449 450 #define INTERRUPT_CONTROL_ICFGX_IMR_MASK (0x2U) 451 #define INTERRUPT_CONTROL_ICFGX_IMR_SHIFT (1U) 452 #define INTERRUPT_CONTROL_ICFGX_IMR_WIDTH (1U) 453 #define INTERRUPT_CONTROL_ICFGX_IMR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFGX_IMR_SHIFT)) & INTERRUPT_CONTROL_ICFGX_IMR_MASK) 454 455 #define INTERRUPT_CONTROL_ICFGX_IMOD_MASK (0xCU) 456 #define INTERRUPT_CONTROL_ICFGX_IMOD_SHIFT (2U) 457 #define INTERRUPT_CONTROL_ICFGX_IMOD_WIDTH (2U) 458 #define INTERRUPT_CONTROL_ICFGX_IMOD(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFGX_IMOD_SHIFT)) & INTERRUPT_CONTROL_ICFGX_IMOD_MASK) 459 460 #define INTERRUPT_CONTROL_ICFGX_IVI_MASK (0x1C0U) 461 #define INTERRUPT_CONTROL_ICFGX_IVI_SHIFT (6U) 462 #define INTERRUPT_CONTROL_ICFGX_IVI_WIDTH (3U) 463 #define INTERRUPT_CONTROL_ICFGX_IVI(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFGX_IVI_SHIFT)) & INTERRUPT_CONTROL_ICFGX_IVI_MASK) 464 465 #define INTERRUPT_CONTROL_ICFGX_IPR_MASK (0x7000U) 466 #define INTERRUPT_CONTROL_ICFGX_IPR_SHIFT (12U) 467 #define INTERRUPT_CONTROL_ICFGX_IPR_WIDTH (3U) 468 #define INTERRUPT_CONTROL_ICFGX_IPR(x) (((uint32_t)(((uint32_t)(x)) << INTERRUPT_CONTROL_ICFGX_IPR_SHIFT)) & INTERRUPT_CONTROL_ICFGX_IPR_MASK) 469 /*! @} */ 470 471 /*! 472 * @} 473 */ /* end of group INTERRUPT_CONTROL_Register_Masks */ 474 475 /*! 476 * @} 477 */ /* end of group INTERRUPT_CONTROL_Peripheral_Access_Layer */ 478 479 #endif /* #if !defined(S32Z2_INTERRUPT_CONTROL_H_) */ 480
