Searched refs:INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX_MASK (Results 1 – 4 of 4) sorted by relevance
23959 #define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX_MASK (0x4000000U) macro23965 …(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX_MASK)
30953 #define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX_MASK (0x4000000U) macro30959 …(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX_MASK)
30949 #define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX_MASK (0x4000000U) macro30955 …(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX_MASK)
30952 #define INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX_MASK (0x4000000U) macro30958 …(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_FLEXSPI1_TX_MASK)
