Searched refs:INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP_MASK (Results 1 – 4 of 4) sorted by relevance
24359 #define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP_MASK (0x200000U) macro24365 …t32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP_MASK)
31353 #define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP_MASK (0x200000U) macro31359 …t32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP_MASK)
31349 #define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP_MASK (0x200000U) macro31355 …t32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP_MASK)
31352 #define INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP_MASK (0x200000U) macro31358 …t32_t)(x)) << INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP_SHIFT)) & INPUTMUX_DMAC0_ITRIG_ENA0_CLR_ACMP_MASK)
