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Searched refs:IMASK2 (Results 1 – 25 of 79) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/flexcan/
Dfsl_flexcan.c484 u32TempIMASK2 = base->IMASK2; in FLEXCAN_EnterFreezeMode()
503 base->IMASK2 = u32TempIMASK2; in FLEXCAN_EnterFreezeMode()
514 u32TempIMASK2 = base->IMASK2; in FLEXCAN_EnterFreezeMode()
540 base->IMASK2 = u32TempIMASK2; in FLEXCAN_EnterFreezeMode()
578 u32TempIMASK2 = base->IMASK2; in FLEXCAN_EnterFreezeMode()
594 base->IMASK2 = u32TempIMASK2; in FLEXCAN_EnterFreezeMode()
4304 tempmask |= ((uint64_t)base->IMASK2) << 32; in FLEXCAN_CheckUnhandleInterruptEvents()
4567 uint32_t intflag[4] = {(base->IMASK1 & base->IFLAG1), (base->IMASK2 & base->IFLAG2), 0U, 0U}; in FLEXCAN_SubHandlerForDataTransfered()
Dfsl_flexcan.h1797 base->IMASK2 |= (uint32_t)(mask >> 32); in FLEXCAN_EnableMbInterrupts()
1845 base->IMASK2 &= ~((uint32_t)(mask >> 32)); in FLEXCAN_DisableMbInterrupts()
/hal_nxp-latest/imx/drivers/
Dflexcan.c442 interruptMaskPtr = &base->IMASK2; in FLEXCAN_SetMsgBufIntCmd()
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K142W_FLEXCAN.h87 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ member
DS32K144W_FLEXCAN.h87 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ member
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_FLEXCAN.h87 __IO uint32_t IMASK2; /**< Interrupt Masks 2, offset: 0x24 */ member
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_FLEXCAN.h87 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ member
/hal_nxp-latest/s32/mcux/devices/S32K344/
DS32K344_device.h30 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ member
/hal_nxp-latest/s32/mcux/devices/S32Z270/
DS32Z270_device.h30 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ member
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h3401 …__IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x… member
3442 #define CAN_IMASK2_REG(base) ((base)->IMASK2)
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h3456 …__IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x… member
3497 #define CAN_IMASK2_REG(base) ((base)->IMASK2)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h3846 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h3866 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h4113 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h4092 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h4116 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h4094 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h4169 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h4251 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h4173 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h17946 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ member
DMIMXRT1175_cm7.h17949 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h17637 __IO uint32_t IMASK2; /**< Interrupt Masks 2 register, offset: 0x24 */ member
DMIMXRT1165_cm4.h17634 __IO uint32_t IMASK2; /**< Interrupt Masks 2 register, offset: 0x24 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h17949 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ member

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