/hal_nxp-latest/mcux/mcux-sdk/drivers/flexcan/ |
D | fsl_flexcan.h | 1796 base->IMASK1 |= (uint32_t)(mask & 0xFFFFFFFFU); in FLEXCAN_EnableMbInterrupts() 1799 base->IMASK1 |= mask; in FLEXCAN_EnableMbInterrupts() 1844 base->IMASK1 &= ~((uint32_t)(mask & 0xFFFFFFFFU)); in FLEXCAN_DisableMbInterrupts() 1847 base->IMASK1 &= ~mask; in FLEXCAN_DisableMbInterrupts()
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D | fsl_flexcan.c | 482 u32TempIMASK1 = base->IMASK1; in FLEXCAN_EnterFreezeMode() 501 base->IMASK1 = u32TempIMASK1; in FLEXCAN_EnterFreezeMode() 512 u32TempIMASK1 = base->IMASK1; in FLEXCAN_EnterFreezeMode() 538 base->IMASK1 = u32TempIMASK1; in FLEXCAN_EnterFreezeMode() 576 u32TempIMASK1 = base->IMASK1; in FLEXCAN_EnterFreezeMode() 592 base->IMASK1 = u32TempIMASK1; in FLEXCAN_EnterFreezeMode() 4301 tempmask = (uint64_t)base->IMASK1; in FLEXCAN_CheckUnhandleInterruptEvents() 4567 uint32_t intflag[4] = {(base->IMASK1 & base->IFLAG1), (base->IMASK2 & base->IFLAG2), 0U, 0U}; in FLEXCAN_SubHandlerForDataTransfered() 4575 uint32_t intflag = base->IMASK1 & base->IFLAG1; in FLEXCAN_SubHandlerForDataTransfered()
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/hal_nxp-latest/imx/drivers/ |
D | flexcan.c | 447 interruptMaskPtr = &base->IMASK1; in FLEXCAN_SetMsgBufIntCmd()
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/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/ |
D | S32K118_FLEXCAN.h | 88 __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ member
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D | S32K142W_FLEXCAN.h | 88 __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ member
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D | S32K142_FLEXCAN.h | 88 __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ member
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D | S32K116_FLEXCAN.h | 88 __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ member
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D | S32K144W_FLEXCAN.h | 88 __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ member
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D | S32K144_FLEXCAN.h | 88 __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ member
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D | S32K146_FLEXCAN.h | 88 __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ member
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D | S32K148_FLEXCAN.h | 88 __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ member
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/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/ |
D | S32Z2_FLEXCAN.h | 88 __IO uint32_t IMASK1; /**< Interrupt Masks 1, offset: 0x28 */ member
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/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/ |
D | S32K344_FLEXCAN.h | 88 __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ member
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/hal_nxp-latest/s32/mcux/devices/S32K344/ |
D | S32K344_device.h | 31 __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ member
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/hal_nxp-latest/s32/mcux/devices/S32Z270/ |
D | S32Z270_device.h | 31 __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MKV11Z7/ |
D | MKV11Z7.h | 749 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/ |
D | MKE18F16.h | 1621 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16F16/ |
D | MKE16F16.h | 1621 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F12/ |
D | MK22F12.h | 3961 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MK24F12/ |
D | MK24F12.h | 4628 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MK63F12/ |
D | MK63F12.h | 4657 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MK64F12/ |
D | MK64F12.h | 4670 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MKV56F24/ |
D | MKV56F24.h | 4995 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MKV58F24/ |
D | MKV58F24.h | 4995 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */ member
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/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/ |
D | MCXA146.h | 1907 __IO uint32_t IMASK1; /**< Interrupt Masks 1, offset: 0x28 */ member
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