Home
last modified time | relevance | path

Searched refs:I3C_MCONFIG_ODHPP_MASK (Results 1 – 25 of 72) sorted by relevance

123

/hal_nxp-latest/mcux/mcux-sdk/drivers/i3c/
Dfsl_i3c.c1106 bool isODHigh = (0U != (base->MCONFIG & I3C_MCONFIG_ODHPP_MASK)) ? true : false; in I3C_MasterSetBaudRate()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC865/
DLPC865.h4803 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
4806 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC864/
DLPC864.h4801 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
4804 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/
DMCXA142.h12398 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
12406 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/
DMCXA143.h12398 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
12406 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/
DMCXA153.h12398 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
12406 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/
DMCXA152.h12398 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
12406 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/
DMCXA146.h15456 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
15462 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/
DMCXA145.h15456 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
15462 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/
DMCXA144.h15456 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
15462 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h10337 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
10340 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
DMIMXRT685S_cm33.h17082 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
17085 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/
DMCXA156.h15460 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
15466 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/
DMCXA154.h15460 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
15466 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/
DMCXA155.h15460 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
15466 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h17082 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
17085 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h19886 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
19889 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
DMIMXRT595S_cm33.h26853 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
26856 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h22088 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
22096 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h22088 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
22096 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h26849 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
26852 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/
DMCXW716A.h16800 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
16803 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h24607 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
24613 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
DMIMXRT735S_cm33_core1.h24651 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
24657 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h26852 #define I3C_MCONFIG_ODHPP_MASK (0x1000000U) macro
26855 … (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)

123