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Searched refs:I3C01FCLKSTCDIV_OFFSET (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_clock.h611 #define I3C01FCLKSTCDIV_OFFSET 0x808 macro
984 …kCLOCK_DivI3cTcClk = CLKCTL1_TUPLE_MUXA(I3C01FCLKSTCDIV_OFFSET, 0), /*!< I3c Tc Clk Divider. …
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_clock.h611 #define I3C01FCLKSTCDIV_OFFSET 0x808 macro
984 …kCLOCK_DivI3cTcClk = CLKCTL1_TUPLE_MUXA(I3C01FCLKSTCDIV_OFFSET, 0), /*!< I3c Tc Clk Divider. …
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_clock.h611 #define I3C01FCLKSTCDIV_OFFSET 0x808 macro
984 …kCLOCK_DivI3cTcClk = CLKCTL1_TUPLE_MUXA(I3C01FCLKSTCDIV_OFFSET, 0), /*!< I3c Tc Clk Divider. …