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Searched refs:I2S_TCR4_SYWD_MASK (Results 1 – 25 of 141) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/sai/
Dfsl_sai.c1039 assert((config->frameSyncWidth - 1UL) <= (I2S_TCR4_SYWD_MASK >> I2S_TCR4_SYWD_SHIFT)); in SAI_TxSetFrameSyncConfig()
1043 tcr4 &= ~(I2S_TCR4_FSE_MASK | I2S_TCR4_FSP_MASK | I2S_TCR4_FSD_MASK | I2S_TCR4_SYWD_MASK); in SAI_TxSetFrameSyncConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC144/
DMCXC144.h3621 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
3624 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC143/
DMCXC143.h3621 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
3624 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC243/
DMCXC243.h3619 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
3622 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC244/
DMCXC244.h3621 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
3624 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F12810/
DMK22F12810.h5871 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
5873 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC444/
DMCXC444.h3621 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
3624 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC443/
DMCXC443.h3621 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
3624 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW22D5/
DMKW22D5.h4168 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
4170 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW24D5/
DMKW24D5.h4168 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
4170 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F25612/
DMK22F25612.h6638 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
6640 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F51212/
DMK22F51212.h6894 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
6896 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F12/
DMK22F12.h10703 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
10705 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK24F12/
DMK24F12.h13380 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
13384 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/
DK32L3A60_cm4.h8316 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
8319 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
DK32L3A60_cm0plus.h7472 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
7475 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK64F12/
DMK64F12.h15211 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
15215 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK63F12/
DMK63F12.h15165 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
15169 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h13427 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
13429 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h13421 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
13423 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h12866 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
12868 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h12864 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
12866 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK26F18/
DMK26F18.h15323 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
15327 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK65F18/
DMK65F18.h17140 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
17144 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK66F18/
DMK66F18.h17140 #define I2S_TCR4_SYWD_MASK (0x1F00U) macro
17144 … (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)

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