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Searched refs:I2S_CFG1_ONECHANNEL_MASK (Results 1 – 25 of 54) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/flexcomm/i2s/
Dfsl_i2s.c526 pcfg1 &= ~I2S_CFG1_ONECHANNEL_MASK; in I2S_EnableSecondaryChannel()
563 …handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT) != 0U … in I2S_TxTransferCreateHandle()
667 …handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT) != 0UL… in I2S_RxTransferCreateHandle()
Dfsl_i2s_dma.c211 if (((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) == 0U)) in I2S_TxTransferCreateHandleDMA()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC51U68/
DLPC51U68.h3809 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
3822 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54114/
DLPC54114_cm0plus.h4013 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
4026 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
DLPC54114_cm4.h4024 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
4037 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54113/
DLPC54113.h4025 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
4038 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54607/
DLPC54607.h5413 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
5426 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S005/
DLPC54S005.h5478 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
5491 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54005/
DLPC54005.h5070 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
5083 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54605/
DLPC54605.h5416 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
5429 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54606/
DLPC54606.h9564 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
9577 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54016/
DLPC54016.h8753 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
8766 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54616/
DLPC54616.h9639 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
9652 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54018M/
DLPC54018M.h9316 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
9329 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54628/
DLPC54628.h9635 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
9648 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5502/
DLPC5502.h13681 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
13694 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5502CPXXXX/
DLPC5502CPXXXX.h13612 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
13625 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54618/
DLPC54618.h9637 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
9650 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S018/
DLPC54S018.h9724 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
9737 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54018/
DLPC54018.h9316 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
9329 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S016/
DLPC54S016.h9118 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
9131 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5504CPXXXX/
DLPC5504CPXXXX.h13612 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
13625 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5504/
DLPC5504.h13681 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
13694 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5506/
DLPC5506.h13681 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
13694 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5506CPXXXX/
DLPC5506CPXXXX.h13612 #define I2S_CFG1_ONECHANNEL_MASK (0x400U) macro
13625 … (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)

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