| /hal_nxp-latest/mcux/mcux-sdk/drivers/snvs_hp/ |
| D | fsl_snvs_hp.h | 560 base->HPLR |= SNVS_HPLR_HAC_L_MASK; in SNVS_HP_LockHighAssuranceCounter()
|
| D | fsl_snvs_hp.c | 563 base->HPLR |= SNVS_HPLR_ZMK_WSL(1); in SNVS_HP_SetLocks()
|
| /hal_nxp-latest/imx/devices/MCIMX6X/ |
| D | MCIMX6X_M4.h | 33408 __IO uint32_t HPLR; /**< , offset: 0x0 */ member
33442 #define SNVS_HPLR_REG(base) ((base)->HPLR)
|
| /hal_nxp-latest/imx/devices/MCIMX7D/ |
| D | MCIMX7D_M4.h | 40144 __IO uint32_t HPLR; /**< , offset: 0x0 */ member
40178 #define SNVS_HPLR_REG(base) ((base)->HPLR)
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/ |
| D | MCIMX7U3_cm4.h | 32202 __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/ |
| D | MCIMX7U5_cm4.h | 32203 __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/ |
| D | MIMXRT1011.h | 26556 __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/ |
| D | MIMXRT1015.h | 29166 __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/ |
| D | MIMXRT1024.h | 34445 __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/ |
| D | MIMXRT1021.h | 34466 __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/ |
| D | MIMXRT1051.h | 36016 __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/ |
| D | MIMXRT1041.h | 37458 __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/ |
| D | MIMXRT1052.h | 40282 __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/ |
| D | MIMXRT1042.h | 40868 __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/ |
| D | MIMXRT1061.h | 38342 __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/ |
| D | MIMXRT1064.h | 42543 __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/ |
| D | MIMX8MQ5_cm4.h | 48973 __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/ |
| D | MIMXRT1062.h | 42536 __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/ |
| D | MIMX8MD7_cm4.h | 51146 __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/ |
| D | MIMX8MD6_cm4.h | 51146 __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/ |
| D | MIMX8MQ6_cm4.h | 51146 __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/ |
| D | MIMX8MQ7_cm4.h | 51146 __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/ |
| D | MIMXRT1175_cm4.h | 66830 __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/ |
| D | MIMXRT1165_cm7.h | 65426 __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/ |
| D | MIMXRT1171.h | 65928 __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ member
|
