| /hal_nxp-latest/mcux/mcux-sdk/drivers/usdhc/ |
| D | fsl_usdhc.h | 1336 … return ((base->HOST_CTRL_CAP & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) != 0UL) ? true : false; in USDHC_RequestTuningForSDR50()
1378 base->HOST_CTRL_CAP &= ~USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK; in USDHC_SetRetuningTimer()
1379 base->HOST_CTRL_CAP |= USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(counter); in USDHC_SetRetuningTimer()
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| D | fsl_usdhc.c | 949 htCapability = base->HOST_CTRL_CAP; in USDHC_GetCapability()
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| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_USDHC.h | 89 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/ |
| D | K32L3A60_cm4.h | 23220 …__I uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
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| D | K32L3A60_cm0plus.h | 23330 …__I uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
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| /hal_nxp-latest/imx/devices/MCIMX6X/ |
| D | MCIMX6X_M4.h | 40294 …__I uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: … member
40338 #define uSDHC_HOST_CTRL_CAP_REG(base) ((base)->HOST_CTRL_CAP)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/ |
| D | MIMXRT685S_dsp.h | 31871 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
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| D | MIMXRT685S_cm33.h | 42827 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
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| /hal_nxp-latest/imx/devices/MCIMX7D/ |
| D | MCIMX7D_M4.h | 43903 …__I uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: … member
43950 #define uSDHC_HOST_CTRL_CAP_REG(base) ((base)->HOST_CTRL_CAP)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/ |
| D | MCIMX7U3_cm4.h | 39208 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/ |
| D | MCIMX7U5_cm4.h | 39209 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/ |
| D | MIMXRT633S.h | 42827 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/ |
| D | MIMXRT595S_dsp.h | 47530 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
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| D | MIMXRT595S_cm33.h | 58575 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/ |
| D | MIMXRT1024.h | 41950 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/ |
| D | MIMXRT1021.h | 41971 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/ |
| D | MIMXRT1051.h | 44032 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/ |
| D | MIMXRT1041.h | 45034 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/ |
| D | MIMXRT1052.h | 48298 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/ |
| D | MIMXRT1042.h | 48444 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/ |
| D | MIMXRT533S.h | 56948 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/ |
| D | MIMXRT1061.h | 46425 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/ |
| D | MIMX8MN5_cm7.h | 53260 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/ |
| D | MIMX8MN2_cm7.h | 53258 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/ |
| D | MIMX8MN4_cm7.h | 53258 …__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ member
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