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Searched refs:HCCR (Results 1 – 25 of 30) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32k1/Mcu/src/
DClock_Ip_Divider.c575 RegValue = IP_SCG->HCCR; in Clock_Ip_SetScgHsrunDivcore_TrustedCall()
578 IP_SCG->HCCR = RegValue; in Clock_Ip_SetScgHsrunDivcore_TrustedCall()
588 RegValue = IP_SCG->HCCR; in Clock_Ip_SetScgHsrunDivbus_TrustedCall()
591 IP_SCG->HCCR = RegValue; in Clock_Ip_SetScgHsrunDivbus_TrustedCall()
601 RegValue = IP_SCG->HCCR; in Clock_Ip_SetScgHsrunDivslow_TrustedCall()
604 IP_SCG->HCCR = RegValue; in Clock_Ip_SetScgHsrunDivslow_TrustedCall()
DClock_Ip_Selector.c553 RegValue = IP_SCG->HCCR; in Clock_Ip_ResetScgHsrunSel_TrustedCall()
556 IP_SCG->HCCR = RegValue; in Clock_Ip_ResetScgHsrunSel_TrustedCall()
563 RegValue = IP_SCG->HCCR; in Clock_Ip_SetScgHsrunSel_TrustedCall()
566 IP_SCG->HCCR = RegValue; in Clock_Ip_SetScgHsrunSel_TrustedCall()
DClock_Ip_Specific.c729 …SelectorConfigurations[SelectorConfigIndex].Value = ClockSource[(IP_SCG->HCCR & SCG_HCCR_SCS_MASK)… in getSelectorConfig()
793 …CoreDividerConfigurations[DividerConfigIndex].Value = ((IP_SCG->HCCR & SCG_HCCR_DIVCORE_MASK) >> S… in getCoreDividerConfig()
859 …BusDividerConfigurations[DividerConfigIndex].Value = ((IP_SCG->HCCR & SCG_HCCR_DIVBUS_MASK) >> SCG… in getBusDividerConfig()
924 …SlowDividerConfigurations[DividerConfigIndex].Value = ((IP_SCG->HCCR & SCG_HCCR_DIVSLOW_MASK) >> S… in getSlowDividerConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/drivers/
Dfsl_clock.h816 SCG->HCCR = *(Config.configInt); in CLOCK_SetHsrunModeSysClkConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/drivers/
Dfsl_clock.h824 SCG->HCCR = *(Config.configInt); in CLOCK_SetHsrunModeSysClkConfig()
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K142_SCG.h79 …__IO uint32_t HCCR; /**< HSRUN Clock Control Register, offset: 0x1C */ member
DS32K146_SCG.h79 …__IO uint32_t HCCR; /**< HSRUN Clock Control Register, offset: 0x1C */ member
DS32K144_SCG.h79 …__IO uint32_t HCCR; /**< HSRUN Clock Control Register, offset: 0x1C */ member
DS32K148_SCG.h79 …__IO uint32_t HCCR; /**< HSRUN Clock Control Register, offset: 0x1C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/drivers/
Dfsl_clock.h823 SCG->HCCR = *(Config.configInt); in CLOCK_SetHsrunModeSysClkConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/drivers/
Dfsl_clock.h834 SCG->HCCR = *(Config.configInt); in CLOCK_SetHsrunModeSysClkConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16F16/drivers/
Dfsl_clock.h834 SCG->HCCR = *(Config.configInt); in CLOCK_SetHsrunModeSysClkConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/drivers/
Dfsl_clock.h828 SCG->HCCR = *(Config.configInt); in CLOCK_SetHsrunModeSysClkConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/drivers/
Dfsl_clock.h890 SCG->HCCR = *(Config.configInt); in CLOCK_SetHsrunModeSysClkConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/drivers/
Dfsl_clock.h890 SCG->HCCR = *(Config.configInt); in CLOCK_SetHsrunModeSysClkConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/drivers/
Dfsl_clock.h982 SCG->HCCR = *(const uint32_t *)(uint32_t)config; in CLOCK_SetHsrunModeSysClkConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/drivers/
Dfsl_clock.h1113 SCG->HCCR = *(const uint32_t *)(uint32_t)config; in CLOCK_SetHsrunModeSysClkConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/drivers/
Dfsl_clock.h1113 SCG->HCCR = *(const uint32_t *)(uint32_t)config; in CLOCK_SetHsrunModeSysClkConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/
DMKE12Z9.h12033 …__IO uint32_t HCCR; /**< HSRUN Clock Control Register, offset: 0x1C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/
DMKE17Z9.h12037 …__IO uint32_t HCCR; /**< HSRUN Clock Control Register, offset: 0x1C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/
DMKE13Z9.h12035 …__IO uint32_t HCCR; /**< HSRUN Clock Control Register, offset: 0x1C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/
DMKE14F16.h15317 …__IO uint32_t HCCR; /**< HSRUN Clock Control Register, offset: 0x1C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h14370 …__IO uint32_t HCCR; /**< HSRUN Clock Control Register, offset: 0x1C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h14370 …__IO uint32_t HCCR; /**< HSRUN Clock Control Register, offset: 0x1C */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/
DMKE18F16.h16323 …__IO uint32_t HCCR; /**< HSRUN Clock Control Register, offset: 0x1C */ member

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