1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_GTMDI.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_GTMDI 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_GTMDI_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_GTMDI_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- GTMDI Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup GTMDI_Peripheral_Access_Layer GTMDI Peripheral Access Layer 68 * @{ 69 */ 70 71 /** GTMDI - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t DID; /**< Device Identity, offset: 0x0 */ 74 uint8_t RESERVED_0[16]; 75 __IO uint32_t DC; /**< GTMDI Development Control, offset: 0x14 */ 76 __I uint32_t DS; /**< GTMDI Development Status, offset: 0x18 */ 77 uint8_t RESERVED_1[16]; 78 __IO uint32_t TIM_WPC1; /**< TIM Watchpoint Control 1, offset: 0x2C */ 79 __IO uint32_t TIM_WPC2; /**< TIM Watchpoint Control 2, offset: 0x30 */ 80 uint8_t RESERVED_2[16]; 81 __IO uint32_t TOM_WPC1; /**< TOM Watchpoint Control 1, offset: 0x44 */ 82 __IO uint32_t TOM_WPC2; /**< TOM Watchpoint Control 2, offset: 0x48 */ 83 uint8_t RESERVED_3[16]; 84 __IO uint32_t ATOM_WPC1; /**< ATOM Watchpoint Control 1, offset: 0x5C */ 85 __IO uint32_t ATOM_WPC2; /**< ATOM Watchpoint Control 2, offset: 0x60 */ 86 uint8_t RESERVED_4[16]; 87 __IO uint32_t SPEA_WPC1; /**< SPEA Watchpoint Control 1, offset: 0x74 */ 88 __IO uint32_t SPEA_WPC2; /**< SPEA Watchpoint Control 2, offset: 0x78 */ 89 uint8_t RESERVED_5[16]; 90 __IO uint32_t SPEB_WPC1; /**< SPEB Watchpoint Control 1, offset: 0x8C */ 91 __IO uint32_t SPEB_WPC2; /**< SPEB Watchpoint Control 2, offset: 0x90 */ 92 uint8_t RESERVED_6[16]; 93 __IO uint32_t DPLL_WPC1; /**< DPLL Watchpoint Control 1, offset: 0xA4 */ 94 __IO uint32_t DPLL_WPC2; /**< DPLL Watchpoint Control 2, offset: 0xA8 */ 95 __IO uint32_t DPLL_WPC3; /**< DPLL Watchpoint Control 3, offset: 0xAC */ 96 __IO uint32_t DPLL_WPC4; /**< DPLL Watchpoint Control 4, offset: 0xB0 */ 97 __IO uint32_t DPLL_WPC5; /**< DPLL Watchpoint Control 5, offset: 0xB4 */ 98 __IO uint32_t DPLL_DTC; /**< DPLL Data Trace Control, offset: 0xB8 */ 99 uint8_t RESERVED_7[12]; 100 __IO uint32_t ARU_WPC1; /**< ARU Watchpoint Control 1, offset: 0xC8 */ 101 __IO uint32_t ARU_WPC2; /**< ARU Watchpoint Control 2, offset: 0xCC */ 102 __IO uint32_t ARU_D0H; /**< ARU Watchpoint DATA0H, offset: 0xD0 */ 103 __IO uint32_t ARU_D0L; /**< ARU Watchpoint DATA0L, offset: 0xD4 */ 104 __IO uint32_t ARU_D1H; /**< ARU Watchpoint DATA1H, offset: 0xD8 */ 105 __IO uint32_t ARU_D1L; /**< ARU Watchpoint ARUD1L, offset: 0xDC */ 106 __IO uint32_t ARU_DTC; /**< ARU Data Trace Control, offset: 0xE0 */ 107 uint8_t RESERVED_8[4]; 108 __IO uint32_t MCS_HBC; /**< MCS Hardware Breakpoint (HBP) Control, offset: 0xE8 */ 109 __IO uint32_t MCS_HLT; /**< MCS Halt Control, offset: 0xEC */ 110 __IO uint32_t MCSA_DC; /**< MCSA Development Control, offset: 0xF0 */ 111 uint8_t RESERVED_9[4]; 112 __IO uint32_t MCSA_WPC; /**< MCSA Watchpoint Control, offset: 0xF8 */ 113 __IO uint32_t MCSA_PTC; /**< MCSA Program Fetch Trace Control, offset: 0xFC */ 114 __IO uint32_t MCSA_DTC; /**< MCSA Data Trace Control, offset: 0x100 */ 115 __IO uint32_t MCSA_WPA1; /**< MCSA Watchpoint Address 1, offset: 0x104 */ 116 __IO uint32_t MCSA_WPA2; /**< MCSA Watchpoint Address 2, offset: 0x108 */ 117 __IO uint32_t MCSA_WPD1; /**< MCSA Watchpoint Data 1, offset: 0x10C */ 118 __IO uint32_t MCSA_WPD2; /**< MCSA Watchpoint Data 2, offset: 0x110 */ 119 __IO uint32_t MCSA_CE; /**< MCSA Channel Enable, offset: 0x114 */ 120 uint8_t RESERVED_10[4]; 121 __IO uint32_t MCSA_DTAR1; /**< MCSA Data Trace Address Range 1, offset: 0x11C */ 122 __IO uint32_t MCSA_DTAR2; /**< MCSA Data Trace Address Range 2, offset: 0x120 */ 123 uint8_t RESERVED_11[16]; 124 __IO uint32_t MCSB_DC; /**< MCSB Development Control, offset: 0x134 */ 125 uint8_t RESERVED_12[4]; 126 __IO uint32_t MCSB_WPC; /**< MCSB Watchpoint Control, offset: 0x13C */ 127 __IO uint32_t MCSB_PTC; /**< MCSB Program Fetch Trace Control, offset: 0x140 */ 128 __IO uint32_t MCSB_DTC; /**< MCSB Data Trace Control, offset: 0x144 */ 129 __IO uint32_t MCSB_WPA1; /**< MCSB Watchpoint Address 1, offset: 0x148 */ 130 __IO uint32_t MCSB_WPA2; /**< MCSB Watchpoint Address 2, offset: 0x14C */ 131 __IO uint32_t MCSB_WPD1; /**< MCSB Watchpoint Data 1, offset: 0x150 */ 132 __IO uint32_t MCSB_WPD2; /**< MCSB Watchpoint Data 2, offset: 0x154 */ 133 __IO uint32_t MCSB_CE; /**< MCSB Channel Enable, offset: 0x158 */ 134 uint8_t RESERVED_13[4]; 135 __IO uint32_t MCSB_DTAR1; /**< MCSB Data Trace Address Range 1, offset: 0x160 */ 136 __IO uint32_t MCSB_DTAR2; /**< MCSB Data Trace Address Range 2, offset: 0x164 */ 137 uint8_t RESERVED_14[16]; 138 __IO uint32_t TBU0_WPC1; /**< TBU0 Watchpoint Control 1, offset: 0x178 */ 139 __IO uint32_t TBU0_WPC2; /**< TBUn Watchpoint Control 2, offset: 0x17C */ 140 __IO uint32_t TBU0_D; /**< TBU0 Watchpoint DATA, offset: 0x180 */ 141 uint8_t RESERVED_15[16]; 142 __IO uint32_t TBU1_WPC1; /**< TBUn Watchpoint Control 1, offset: 0x194 */ 143 __IO uint32_t TBU1_WPC2; /**< TBUn Watchpoint Control 2, offset: 0x198 */ 144 __IO uint32_t TBU1_D; /**< TBUn Watchpoint DATA, offset: 0x19C */ 145 uint8_t RESERVED_16[16]; 146 __IO uint32_t TBU2_WPC1; /**< TBUn Watchpoint Control 1, offset: 0x1B0 */ 147 __IO uint32_t TBU2_WPC2; /**< TBUn Watchpoint Control 2, offset: 0x1B4 */ 148 __IO uint32_t TBU2_D; /**< TBUn Watchpoint DATA, offset: 0x1B8 */ 149 uint8_t RESERVED_17[16]; 150 __IO uint32_t TBU3_WPC1; /**< TBUn Watchpoint Control 1, offset: 0x1CC */ 151 __IO uint32_t TBU3_WPC2; /**< TBUn Watchpoint Control 2, offset: 0x1D0 */ 152 __IO uint32_t TBU3_D; /**< TBUn Watchpoint DATA, offset: 0x1D4 */ 153 uint8_t RESERVED_18[16]; 154 __IO uint32_t TIO_IN_WPC1; /**< TIO IN watchpoint control register 1, offset: 0x1E8 */ 155 __IO uint32_t TIO_IN_WPC2; /**< TIO IN watchpoint control register 2, offset: 0x1EC */ 156 uint8_t RESERVED_19[16]; 157 __IO uint32_t TIO_OUT_WPC1; /**< TIO OUT Watchpoint Control 1, offset: 0x200 */ 158 __IO uint32_t TIO_OUT_WPC2; /**< TIO OUT Watchpoint Control 2, offset: 0x204 */ 159 uint8_t RESERVED_20[352]; 160 __IO uint32_t ATID; /**< ATB Bus ID Control, offset: 0x368 */ 161 uint8_t RESERVED_21[3152]; 162 __I uint32_t DEVARCH; /**< Device Architecture, offset: 0xFBC */ 163 uint8_t RESERVED_22[12]; 164 __I uint32_t DEVTYPE; /**< Device Type Identifier, offset: 0xFCC */ 165 __I uint32_t PIDR4; /**< Peripheral Identification 4, offset: 0xFD0 */ 166 uint32_t PIDR5; /**< Peripheral Identification 5, offset: 0xFD4 */ 167 uint32_t PIDR6; /**< Peripheral Identification 6, offset: 0xFD8 */ 168 uint32_t PIDR7; /**< Peripheral Identification 7, offset: 0xFDC */ 169 __I uint32_t PIDR0; /**< Peripheral Identification 0, offset: 0xFE0 */ 170 __I uint32_t PIDR1; /**< Peripheral Identification 1, offset: 0xFE4 */ 171 __I uint32_t PIDR2; /**< Peripheral Identification 2, offset: 0xFE8 */ 172 __I uint32_t PIDR3; /**< Peripheral Identification 3, offset: 0xFEC */ 173 __I uint32_t CIDR0; /**< Component Identification 0, offset: 0xFF0 */ 174 __I uint32_t CIDR1; /**< Component Identification 1, offset: 0xFF4 */ 175 __I uint32_t CIDR2; /**< Component Identification 2, offset: 0xFF8 */ 176 __I uint32_t CIDR3; /**< Component Identification 3, offset: 0xFFC */ 177 } GTMDI_Type, *GTMDI_MemMapPtr; 178 179 /** Number of instances of the GTMDI module. */ 180 #define GTMDI_INSTANCE_COUNT (1u) 181 182 /* GTMDI - Peripheral instance base addresses */ 183 /** Peripheral GTMDI base address */ 184 #define IP_GTMDI_BASE (0x4D480000u) 185 /** Peripheral GTMDI base pointer */ 186 #define IP_GTMDI ((GTMDI_Type *)IP_GTMDI_BASE) 187 /** Array initializer of GTMDI peripheral base addresses */ 188 #define IP_GTMDI_BASE_ADDRS { IP_GTMDI_BASE } 189 /** Array initializer of GTMDI peripheral base pointers */ 190 #define IP_GTMDI_BASE_PTRS { IP_GTMDI } 191 192 /* ---------------------------------------------------------------------------- 193 -- GTMDI Register Masks 194 ---------------------------------------------------------------------------- */ 195 196 /*! 197 * @addtogroup GTMDI_Register_Masks GTMDI Register Masks 198 * @{ 199 */ 200 201 /*! @name DID - Device Identity */ 202 /*! @{ */ 203 204 #define GTMDI_DID_IDCODE_MASK (0x1U) 205 #define GTMDI_DID_IDCODE_SHIFT (0U) 206 #define GTMDI_DID_IDCODE_WIDTH (1U) 207 #define GTMDI_DID_IDCODE(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DID_IDCODE_SHIFT)) & GTMDI_DID_IDCODE_MASK) 208 209 #define GTMDI_DID_MIC_MASK (0xFFEU) 210 #define GTMDI_DID_MIC_SHIFT (1U) 211 #define GTMDI_DID_MIC_WIDTH (11U) 212 #define GTMDI_DID_MIC(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DID_MIC_SHIFT)) & GTMDI_DID_MIC_MASK) 213 214 #define GTMDI_DID_PIN_MASK (0x3FF000U) 215 #define GTMDI_DID_PIN_SHIFT (12U) 216 #define GTMDI_DID_PIN_WIDTH (10U) 217 #define GTMDI_DID_PIN(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DID_PIN_SHIFT)) & GTMDI_DID_PIN_MASK) 218 219 #define GTMDI_DID_DC_MASK (0xFC00000U) 220 #define GTMDI_DID_DC_SHIFT (22U) 221 #define GTMDI_DID_DC_WIDTH (6U) 222 #define GTMDI_DID_DC(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DID_DC_SHIFT)) & GTMDI_DID_DC_MASK) 223 224 #define GTMDI_DID_PRN_MASK (0xF0000000U) 225 #define GTMDI_DID_PRN_SHIFT (28U) 226 #define GTMDI_DID_PRN_WIDTH (4U) 227 #define GTMDI_DID_PRN(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DID_PRN_SHIFT)) & GTMDI_DID_PRN_MASK) 228 /*! @} */ 229 230 /*! @name DC - GTMDI Development Control */ 231 /*! @{ */ 232 233 #define GTMDI_DC_TSFT_MASK (0x1U) 234 #define GTMDI_DC_TSFT_SHIFT (0U) 235 #define GTMDI_DC_TSFT_WIDTH (1U) 236 #define GTMDI_DC_TSFT(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DC_TSFT_SHIFT)) & GTMDI_DC_TSFT_MASK) 237 238 #define GTMDI_DC_SDBE_MASK (0x4U) 239 #define GTMDI_DC_SDBE_SHIFT (2U) 240 #define GTMDI_DC_SDBE_WIDTH (1U) 241 #define GTMDI_DC_SDBE(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DC_SDBE_SHIFT)) & GTMDI_DC_SDBE_MASK) 242 243 #define GTMDI_DC_DBR_MASK (0x8U) 244 #define GTMDI_DC_DBR_SHIFT (3U) 245 #define GTMDI_DC_DBR_WIDTH (1U) 246 #define GTMDI_DC_DBR(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DC_DBR_SHIFT)) & GTMDI_DC_DBR_MASK) 247 248 #define GTMDI_DC_DBE_MASK (0x10U) 249 #define GTMDI_DC_DBE_SHIFT (4U) 250 #define GTMDI_DC_DBE_WIDTH (1U) 251 #define GTMDI_DC_DBE(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DC_DBE_SHIFT)) & GTMDI_DC_DBE_MASK) 252 253 #define GTMDI_DC_CHR_MASK (0x100U) 254 #define GTMDI_DC_CHR_SHIFT (8U) 255 #define GTMDI_DC_CHR_WIDTH (1U) 256 #define GTMDI_DC_CHR(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DC_CHR_SHIFT)) & GTMDI_DC_CHR_MASK) 257 258 #define GTMDI_DC_EOS1_MASK (0x1F0000U) 259 #define GTMDI_DC_EOS1_SHIFT (16U) 260 #define GTMDI_DC_EOS1_WIDTH (5U) 261 #define GTMDI_DC_EOS1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DC_EOS1_SHIFT)) & GTMDI_DC_EOS1_MASK) 262 263 #define GTMDI_DC_EOS0_MASK (0x1F000000U) 264 #define GTMDI_DC_EOS0_SHIFT (24U) 265 #define GTMDI_DC_EOS0_WIDTH (5U) 266 #define GTMDI_DC_EOS0(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DC_EOS0_SHIFT)) & GTMDI_DC_EOS0_MASK) 267 268 #define GTMDI_DC_GDE_MASK (0x80000000U) 269 #define GTMDI_DC_GDE_SHIFT (31U) 270 #define GTMDI_DC_GDE_WIDTH (1U) 271 #define GTMDI_DC_GDE(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DC_GDE_SHIFT)) & GTMDI_DC_GDE_MASK) 272 /*! @} */ 273 274 /*! @name DS - GTMDI Development Status */ 275 /*! @{ */ 276 277 #define GTMDI_DS_HS2_MASK (0xFFFFU) 278 #define GTMDI_DS_HS2_SHIFT (0U) 279 #define GTMDI_DS_HS2_WIDTH (16U) 280 #define GTMDI_DS_HS2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DS_HS2_SHIFT)) & GTMDI_DS_HS2_MASK) 281 282 #define GTMDI_DS_HS1_MASK (0x7FFF0000U) 283 #define GTMDI_DS_HS1_SHIFT (16U) 284 #define GTMDI_DS_HS1_WIDTH (15U) 285 #define GTMDI_DS_HS1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DS_HS1_SHIFT)) & GTMDI_DS_HS1_MASK) 286 287 #define GTMDI_DS_HLT_MASK (0x80000000U) 288 #define GTMDI_DS_HLT_SHIFT (31U) 289 #define GTMDI_DS_HLT_WIDTH (1U) 290 #define GTMDI_DS_HLT(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DS_HLT_SHIFT)) & GTMDI_DS_HLT_MASK) 291 /*! @} */ 292 293 /*! @name TIM_WPC1 - TIM Watchpoint Control 1 */ 294 /*! @{ */ 295 296 #define GTMDI_TIM_WPC1_CHSEL2_MASK (0x7U) 297 #define GTMDI_TIM_WPC1_CHSEL2_SHIFT (0U) 298 #define GTMDI_TIM_WPC1_CHSEL2_WIDTH (3U) 299 #define GTMDI_TIM_WPC1_CHSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIM_WPC1_CHSEL2_SHIFT)) & GTMDI_TIM_WPC1_CHSEL2_MASK) 300 301 #define GTMDI_TIM_WPC1_WMC2_MASK (0x40U) 302 #define GTMDI_TIM_WPC1_WMC2_SHIFT (6U) 303 #define GTMDI_TIM_WPC1_WMC2_WIDTH (1U) 304 #define GTMDI_TIM_WPC1_WMC2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIM_WPC1_WMC2_SHIFT)) & GTMDI_TIM_WPC1_WMC2_MASK) 305 306 #define GTMDI_TIM_WPC1_HEN2_MASK (0x80U) 307 #define GTMDI_TIM_WPC1_HEN2_SHIFT (7U) 308 #define GTMDI_TIM_WPC1_HEN2_WIDTH (1U) 309 #define GTMDI_TIM_WPC1_HEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIM_WPC1_HEN2_SHIFT)) & GTMDI_TIM_WPC1_HEN2_MASK) 310 311 #define GTMDI_TIM_WPC1_SSEL2_MASK (0x700U) 312 #define GTMDI_TIM_WPC1_SSEL2_SHIFT (8U) 313 #define GTMDI_TIM_WPC1_SSEL2_WIDTH (3U) 314 #define GTMDI_TIM_WPC1_SSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIM_WPC1_SSEL2_SHIFT)) & GTMDI_TIM_WPC1_SSEL2_MASK) 315 316 #define GTMDI_TIM_WPC1_TSS2_MASK (0x3000U) 317 #define GTMDI_TIM_WPC1_TSS2_SHIFT (12U) 318 #define GTMDI_TIM_WPC1_TSS2_WIDTH (2U) 319 #define GTMDI_TIM_WPC1_TSS2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIM_WPC1_TSS2_SHIFT)) & GTMDI_TIM_WPC1_TSS2_MASK) 320 321 #define GTMDI_TIM_WPC1_CHSEL1_MASK (0x70000U) 322 #define GTMDI_TIM_WPC1_CHSEL1_SHIFT (16U) 323 #define GTMDI_TIM_WPC1_CHSEL1_WIDTH (3U) 324 #define GTMDI_TIM_WPC1_CHSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIM_WPC1_CHSEL1_SHIFT)) & GTMDI_TIM_WPC1_CHSEL1_MASK) 325 326 #define GTMDI_TIM_WPC1_WMC1_MASK (0x400000U) 327 #define GTMDI_TIM_WPC1_WMC1_SHIFT (22U) 328 #define GTMDI_TIM_WPC1_WMC1_WIDTH (1U) 329 #define GTMDI_TIM_WPC1_WMC1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIM_WPC1_WMC1_SHIFT)) & GTMDI_TIM_WPC1_WMC1_MASK) 330 331 #define GTMDI_TIM_WPC1_HEN1_MASK (0x800000U) 332 #define GTMDI_TIM_WPC1_HEN1_SHIFT (23U) 333 #define GTMDI_TIM_WPC1_HEN1_WIDTH (1U) 334 #define GTMDI_TIM_WPC1_HEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIM_WPC1_HEN1_SHIFT)) & GTMDI_TIM_WPC1_HEN1_MASK) 335 336 #define GTMDI_TIM_WPC1_SSEL1_MASK (0x7000000U) 337 #define GTMDI_TIM_WPC1_SSEL1_SHIFT (24U) 338 #define GTMDI_TIM_WPC1_SSEL1_WIDTH (3U) 339 #define GTMDI_TIM_WPC1_SSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIM_WPC1_SSEL1_SHIFT)) & GTMDI_TIM_WPC1_SSEL1_MASK) 340 341 #define GTMDI_TIM_WPC1_TSS1_MASK (0x30000000U) 342 #define GTMDI_TIM_WPC1_TSS1_SHIFT (28U) 343 #define GTMDI_TIM_WPC1_TSS1_WIDTH (2U) 344 #define GTMDI_TIM_WPC1_TSS1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIM_WPC1_TSS1_SHIFT)) & GTMDI_TIM_WPC1_TSS1_MASK) 345 /*! @} */ 346 347 /*! @name TIM_WPC2 - TIM Watchpoint Control 2 */ 348 /*! @{ */ 349 350 #define GTMDI_TIM_WPC2_SEN2_MASK (0x1U) 351 #define GTMDI_TIM_WPC2_SEN2_SHIFT (0U) 352 #define GTMDI_TIM_WPC2_SEN2_WIDTH (1U) 353 #define GTMDI_TIM_WPC2_SEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIM_WPC2_SEN2_SHIFT)) & GTMDI_TIM_WPC2_SEN2_MASK) 354 355 #define GTMDI_TIM_WPC2_TEN2_MASK (0x2U) 356 #define GTMDI_TIM_WPC2_TEN2_SHIFT (1U) 357 #define GTMDI_TIM_WPC2_TEN2_WIDTH (1U) 358 #define GTMDI_TIM_WPC2_TEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIM_WPC2_TEN2_SHIFT)) & GTMDI_TIM_WPC2_TEN2_MASK) 359 360 #define GTMDI_TIM_WPC2_STSEL2_MASK (0x30U) 361 #define GTMDI_TIM_WPC2_STSEL2_SHIFT (4U) 362 #define GTMDI_TIM_WPC2_STSEL2_WIDTH (2U) 363 #define GTMDI_TIM_WPC2_STSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIM_WPC2_STSEL2_SHIFT)) & GTMDI_TIM_WPC2_STSEL2_MASK) 364 365 #define GTMDI_TIM_WPC2_WTSEL2_MASK (0x7000U) 366 #define GTMDI_TIM_WPC2_WTSEL2_SHIFT (12U) 367 #define GTMDI_TIM_WPC2_WTSEL2_WIDTH (3U) 368 #define GTMDI_TIM_WPC2_WTSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIM_WPC2_WTSEL2_SHIFT)) & GTMDI_TIM_WPC2_WTSEL2_MASK) 369 370 #define GTMDI_TIM_WPC2_SEN1_MASK (0x10000U) 371 #define GTMDI_TIM_WPC2_SEN1_SHIFT (16U) 372 #define GTMDI_TIM_WPC2_SEN1_WIDTH (1U) 373 #define GTMDI_TIM_WPC2_SEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIM_WPC2_SEN1_SHIFT)) & GTMDI_TIM_WPC2_SEN1_MASK) 374 375 #define GTMDI_TIM_WPC2_TEN1_MASK (0x20000U) 376 #define GTMDI_TIM_WPC2_TEN1_SHIFT (17U) 377 #define GTMDI_TIM_WPC2_TEN1_WIDTH (1U) 378 #define GTMDI_TIM_WPC2_TEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIM_WPC2_TEN1_SHIFT)) & GTMDI_TIM_WPC2_TEN1_MASK) 379 380 #define GTMDI_TIM_WPC2_STSEL1_MASK (0x300000U) 381 #define GTMDI_TIM_WPC2_STSEL1_SHIFT (20U) 382 #define GTMDI_TIM_WPC2_STSEL1_WIDTH (2U) 383 #define GTMDI_TIM_WPC2_STSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIM_WPC2_STSEL1_SHIFT)) & GTMDI_TIM_WPC2_STSEL1_MASK) 384 385 #define GTMDI_TIM_WPC2_WTSEL1_MASK (0x70000000U) 386 #define GTMDI_TIM_WPC2_WTSEL1_SHIFT (28U) 387 #define GTMDI_TIM_WPC2_WTSEL1_WIDTH (3U) 388 #define GTMDI_TIM_WPC2_WTSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIM_WPC2_WTSEL1_SHIFT)) & GTMDI_TIM_WPC2_WTSEL1_MASK) 389 /*! @} */ 390 391 /*! @name TOM_WPC1 - TOM Watchpoint Control 1 */ 392 /*! @{ */ 393 394 #define GTMDI_TOM_WPC1_CHSEL2_MASK (0xFU) 395 #define GTMDI_TOM_WPC1_CHSEL2_SHIFT (0U) 396 #define GTMDI_TOM_WPC1_CHSEL2_WIDTH (4U) 397 #define GTMDI_TOM_WPC1_CHSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TOM_WPC1_CHSEL2_SHIFT)) & GTMDI_TOM_WPC1_CHSEL2_MASK) 398 399 #define GTMDI_TOM_WPC1_WMC2_MASK (0x40U) 400 #define GTMDI_TOM_WPC1_WMC2_SHIFT (6U) 401 #define GTMDI_TOM_WPC1_WMC2_WIDTH (1U) 402 #define GTMDI_TOM_WPC1_WMC2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TOM_WPC1_WMC2_SHIFT)) & GTMDI_TOM_WPC1_WMC2_MASK) 403 404 #define GTMDI_TOM_WPC1_HEN2_MASK (0x80U) 405 #define GTMDI_TOM_WPC1_HEN2_SHIFT (7U) 406 #define GTMDI_TOM_WPC1_HEN2_WIDTH (1U) 407 #define GTMDI_TOM_WPC1_HEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TOM_WPC1_HEN2_SHIFT)) & GTMDI_TOM_WPC1_HEN2_MASK) 408 409 #define GTMDI_TOM_WPC1_SSEL2_MASK (0x700U) 410 #define GTMDI_TOM_WPC1_SSEL2_SHIFT (8U) 411 #define GTMDI_TOM_WPC1_SSEL2_WIDTH (3U) 412 #define GTMDI_TOM_WPC1_SSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TOM_WPC1_SSEL2_SHIFT)) & GTMDI_TOM_WPC1_SSEL2_MASK) 413 414 #define GTMDI_TOM_WPC1_TSS2_MASK (0x3000U) 415 #define GTMDI_TOM_WPC1_TSS2_SHIFT (12U) 416 #define GTMDI_TOM_WPC1_TSS2_WIDTH (2U) 417 #define GTMDI_TOM_WPC1_TSS2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TOM_WPC1_TSS2_SHIFT)) & GTMDI_TOM_WPC1_TSS2_MASK) 418 419 #define GTMDI_TOM_WPC1_POL2_MASK (0x8000U) 420 #define GTMDI_TOM_WPC1_POL2_SHIFT (15U) 421 #define GTMDI_TOM_WPC1_POL2_WIDTH (1U) 422 #define GTMDI_TOM_WPC1_POL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TOM_WPC1_POL2_SHIFT)) & GTMDI_TOM_WPC1_POL2_MASK) 423 424 #define GTMDI_TOM_WPC1_CHSEL1_MASK (0xF0000U) 425 #define GTMDI_TOM_WPC1_CHSEL1_SHIFT (16U) 426 #define GTMDI_TOM_WPC1_CHSEL1_WIDTH (4U) 427 #define GTMDI_TOM_WPC1_CHSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TOM_WPC1_CHSEL1_SHIFT)) & GTMDI_TOM_WPC1_CHSEL1_MASK) 428 429 #define GTMDI_TOM_WPC1_WMC1_MASK (0x400000U) 430 #define GTMDI_TOM_WPC1_WMC1_SHIFT (22U) 431 #define GTMDI_TOM_WPC1_WMC1_WIDTH (1U) 432 #define GTMDI_TOM_WPC1_WMC1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TOM_WPC1_WMC1_SHIFT)) & GTMDI_TOM_WPC1_WMC1_MASK) 433 434 #define GTMDI_TOM_WPC1_HEN1_MASK (0x800000U) 435 #define GTMDI_TOM_WPC1_HEN1_SHIFT (23U) 436 #define GTMDI_TOM_WPC1_HEN1_WIDTH (1U) 437 #define GTMDI_TOM_WPC1_HEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TOM_WPC1_HEN1_SHIFT)) & GTMDI_TOM_WPC1_HEN1_MASK) 438 439 #define GTMDI_TOM_WPC1_SSEL1_MASK (0x7000000U) 440 #define GTMDI_TOM_WPC1_SSEL1_SHIFT (24U) 441 #define GTMDI_TOM_WPC1_SSEL1_WIDTH (3U) 442 #define GTMDI_TOM_WPC1_SSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TOM_WPC1_SSEL1_SHIFT)) & GTMDI_TOM_WPC1_SSEL1_MASK) 443 444 #define GTMDI_TOM_WPC1_TSS1_MASK (0x30000000U) 445 #define GTMDI_TOM_WPC1_TSS1_SHIFT (28U) 446 #define GTMDI_TOM_WPC1_TSS1_WIDTH (2U) 447 #define GTMDI_TOM_WPC1_TSS1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TOM_WPC1_TSS1_SHIFT)) & GTMDI_TOM_WPC1_TSS1_MASK) 448 449 #define GTMDI_TOM_WPC1_POL1_MASK (0x80000000U) 450 #define GTMDI_TOM_WPC1_POL1_SHIFT (31U) 451 #define GTMDI_TOM_WPC1_POL1_WIDTH (1U) 452 #define GTMDI_TOM_WPC1_POL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TOM_WPC1_POL1_SHIFT)) & GTMDI_TOM_WPC1_POL1_MASK) 453 /*! @} */ 454 455 /*! @name TOM_WPC2 - TOM Watchpoint Control 2 */ 456 /*! @{ */ 457 458 #define GTMDI_TOM_WPC2_SEN2_MASK (0x1U) 459 #define GTMDI_TOM_WPC2_SEN2_SHIFT (0U) 460 #define GTMDI_TOM_WPC2_SEN2_WIDTH (1U) 461 #define GTMDI_TOM_WPC2_SEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TOM_WPC2_SEN2_SHIFT)) & GTMDI_TOM_WPC2_SEN2_MASK) 462 463 #define GTMDI_TOM_WPC2_TEN2_MASK (0x2U) 464 #define GTMDI_TOM_WPC2_TEN2_SHIFT (1U) 465 #define GTMDI_TOM_WPC2_TEN2_WIDTH (1U) 466 #define GTMDI_TOM_WPC2_TEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TOM_WPC2_TEN2_SHIFT)) & GTMDI_TOM_WPC2_TEN2_MASK) 467 468 #define GTMDI_TOM_WPC2_STSEL2_MASK (0x30U) 469 #define GTMDI_TOM_WPC2_STSEL2_SHIFT (4U) 470 #define GTMDI_TOM_WPC2_STSEL2_WIDTH (2U) 471 #define GTMDI_TOM_WPC2_STSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TOM_WPC2_STSEL2_SHIFT)) & GTMDI_TOM_WPC2_STSEL2_MASK) 472 473 #define GTMDI_TOM_WPC2_WTSEL2_MASK (0x7000U) 474 #define GTMDI_TOM_WPC2_WTSEL2_SHIFT (12U) 475 #define GTMDI_TOM_WPC2_WTSEL2_WIDTH (3U) 476 #define GTMDI_TOM_WPC2_WTSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TOM_WPC2_WTSEL2_SHIFT)) & GTMDI_TOM_WPC2_WTSEL2_MASK) 477 478 #define GTMDI_TOM_WPC2_SEN1_MASK (0x10000U) 479 #define GTMDI_TOM_WPC2_SEN1_SHIFT (16U) 480 #define GTMDI_TOM_WPC2_SEN1_WIDTH (1U) 481 #define GTMDI_TOM_WPC2_SEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TOM_WPC2_SEN1_SHIFT)) & GTMDI_TOM_WPC2_SEN1_MASK) 482 483 #define GTMDI_TOM_WPC2_TEN1_MASK (0x20000U) 484 #define GTMDI_TOM_WPC2_TEN1_SHIFT (17U) 485 #define GTMDI_TOM_WPC2_TEN1_WIDTH (1U) 486 #define GTMDI_TOM_WPC2_TEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TOM_WPC2_TEN1_SHIFT)) & GTMDI_TOM_WPC2_TEN1_MASK) 487 488 #define GTMDI_TOM_WPC2_STSEL1_MASK (0x300000U) 489 #define GTMDI_TOM_WPC2_STSEL1_SHIFT (20U) 490 #define GTMDI_TOM_WPC2_STSEL1_WIDTH (2U) 491 #define GTMDI_TOM_WPC2_STSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TOM_WPC2_STSEL1_SHIFT)) & GTMDI_TOM_WPC2_STSEL1_MASK) 492 493 #define GTMDI_TOM_WPC2_WTSEL1_MASK (0x70000000U) 494 #define GTMDI_TOM_WPC2_WTSEL1_SHIFT (28U) 495 #define GTMDI_TOM_WPC2_WTSEL1_WIDTH (3U) 496 #define GTMDI_TOM_WPC2_WTSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TOM_WPC2_WTSEL1_SHIFT)) & GTMDI_TOM_WPC2_WTSEL1_MASK) 497 /*! @} */ 498 499 /*! @name ATOM_WPC1 - ATOM Watchpoint Control 1 */ 500 /*! @{ */ 501 502 #define GTMDI_ATOM_WPC1_CHSEL2_MASK (0x7U) 503 #define GTMDI_ATOM_WPC1_CHSEL2_SHIFT (0U) 504 #define GTMDI_ATOM_WPC1_CHSEL2_WIDTH (3U) 505 #define GTMDI_ATOM_WPC1_CHSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ATOM_WPC1_CHSEL2_SHIFT)) & GTMDI_ATOM_WPC1_CHSEL2_MASK) 506 507 #define GTMDI_ATOM_WPC1_WMC2_MASK (0x40U) 508 #define GTMDI_ATOM_WPC1_WMC2_SHIFT (6U) 509 #define GTMDI_ATOM_WPC1_WMC2_WIDTH (1U) 510 #define GTMDI_ATOM_WPC1_WMC2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ATOM_WPC1_WMC2_SHIFT)) & GTMDI_ATOM_WPC1_WMC2_MASK) 511 512 #define GTMDI_ATOM_WPC1_HEN2_MASK (0x80U) 513 #define GTMDI_ATOM_WPC1_HEN2_SHIFT (7U) 514 #define GTMDI_ATOM_WPC1_HEN2_WIDTH (1U) 515 #define GTMDI_ATOM_WPC1_HEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ATOM_WPC1_HEN2_SHIFT)) & GTMDI_ATOM_WPC1_HEN2_MASK) 516 517 #define GTMDI_ATOM_WPC1_SSEL2_MASK (0xF00U) 518 #define GTMDI_ATOM_WPC1_SSEL2_SHIFT (8U) 519 #define GTMDI_ATOM_WPC1_SSEL2_WIDTH (4U) 520 #define GTMDI_ATOM_WPC1_SSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ATOM_WPC1_SSEL2_SHIFT)) & GTMDI_ATOM_WPC1_SSEL2_MASK) 521 522 #define GTMDI_ATOM_WPC1_TSS2_MASK (0x3000U) 523 #define GTMDI_ATOM_WPC1_TSS2_SHIFT (12U) 524 #define GTMDI_ATOM_WPC1_TSS2_WIDTH (2U) 525 #define GTMDI_ATOM_WPC1_TSS2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ATOM_WPC1_TSS2_SHIFT)) & GTMDI_ATOM_WPC1_TSS2_MASK) 526 527 #define GTMDI_ATOM_WPC1_POL2_MASK (0x8000U) 528 #define GTMDI_ATOM_WPC1_POL2_SHIFT (15U) 529 #define GTMDI_ATOM_WPC1_POL2_WIDTH (1U) 530 #define GTMDI_ATOM_WPC1_POL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ATOM_WPC1_POL2_SHIFT)) & GTMDI_ATOM_WPC1_POL2_MASK) 531 532 #define GTMDI_ATOM_WPC1_CHSEL1_MASK (0x70000U) 533 #define GTMDI_ATOM_WPC1_CHSEL1_SHIFT (16U) 534 #define GTMDI_ATOM_WPC1_CHSEL1_WIDTH (3U) 535 #define GTMDI_ATOM_WPC1_CHSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ATOM_WPC1_CHSEL1_SHIFT)) & GTMDI_ATOM_WPC1_CHSEL1_MASK) 536 537 #define GTMDI_ATOM_WPC1_WMC1_MASK (0x400000U) 538 #define GTMDI_ATOM_WPC1_WMC1_SHIFT (22U) 539 #define GTMDI_ATOM_WPC1_WMC1_WIDTH (1U) 540 #define GTMDI_ATOM_WPC1_WMC1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ATOM_WPC1_WMC1_SHIFT)) & GTMDI_ATOM_WPC1_WMC1_MASK) 541 542 #define GTMDI_ATOM_WPC1_HEN1_MASK (0x800000U) 543 #define GTMDI_ATOM_WPC1_HEN1_SHIFT (23U) 544 #define GTMDI_ATOM_WPC1_HEN1_WIDTH (1U) 545 #define GTMDI_ATOM_WPC1_HEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ATOM_WPC1_HEN1_SHIFT)) & GTMDI_ATOM_WPC1_HEN1_MASK) 546 547 #define GTMDI_ATOM_WPC1_SSEL1_MASK (0xF000000U) 548 #define GTMDI_ATOM_WPC1_SSEL1_SHIFT (24U) 549 #define GTMDI_ATOM_WPC1_SSEL1_WIDTH (4U) 550 #define GTMDI_ATOM_WPC1_SSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ATOM_WPC1_SSEL1_SHIFT)) & GTMDI_ATOM_WPC1_SSEL1_MASK) 551 552 #define GTMDI_ATOM_WPC1_TSS1_MASK (0x30000000U) 553 #define GTMDI_ATOM_WPC1_TSS1_SHIFT (28U) 554 #define GTMDI_ATOM_WPC1_TSS1_WIDTH (2U) 555 #define GTMDI_ATOM_WPC1_TSS1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ATOM_WPC1_TSS1_SHIFT)) & GTMDI_ATOM_WPC1_TSS1_MASK) 556 557 #define GTMDI_ATOM_WPC1_POL1_MASK (0x80000000U) 558 #define GTMDI_ATOM_WPC1_POL1_SHIFT (31U) 559 #define GTMDI_ATOM_WPC1_POL1_WIDTH (1U) 560 #define GTMDI_ATOM_WPC1_POL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ATOM_WPC1_POL1_SHIFT)) & GTMDI_ATOM_WPC1_POL1_MASK) 561 /*! @} */ 562 563 /*! @name ATOM_WPC2 - ATOM Watchpoint Control 2 */ 564 /*! @{ */ 565 566 #define GTMDI_ATOM_WPC2_SEN2_MASK (0x1U) 567 #define GTMDI_ATOM_WPC2_SEN2_SHIFT (0U) 568 #define GTMDI_ATOM_WPC2_SEN2_WIDTH (1U) 569 #define GTMDI_ATOM_WPC2_SEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ATOM_WPC2_SEN2_SHIFT)) & GTMDI_ATOM_WPC2_SEN2_MASK) 570 571 #define GTMDI_ATOM_WPC2_TEN2_MASK (0x2U) 572 #define GTMDI_ATOM_WPC2_TEN2_SHIFT (1U) 573 #define GTMDI_ATOM_WPC2_TEN2_WIDTH (1U) 574 #define GTMDI_ATOM_WPC2_TEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ATOM_WPC2_TEN2_SHIFT)) & GTMDI_ATOM_WPC2_TEN2_MASK) 575 576 #define GTMDI_ATOM_WPC2_STSEL2_MASK (0x30U) 577 #define GTMDI_ATOM_WPC2_STSEL2_SHIFT (4U) 578 #define GTMDI_ATOM_WPC2_STSEL2_WIDTH (2U) 579 #define GTMDI_ATOM_WPC2_STSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ATOM_WPC2_STSEL2_SHIFT)) & GTMDI_ATOM_WPC2_STSEL2_MASK) 580 581 #define GTMDI_ATOM_WPC2_WTSEL2_MASK (0x7000U) 582 #define GTMDI_ATOM_WPC2_WTSEL2_SHIFT (12U) 583 #define GTMDI_ATOM_WPC2_WTSEL2_WIDTH (3U) 584 #define GTMDI_ATOM_WPC2_WTSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ATOM_WPC2_WTSEL2_SHIFT)) & GTMDI_ATOM_WPC2_WTSEL2_MASK) 585 586 #define GTMDI_ATOM_WPC2_SEN1_MASK (0x10000U) 587 #define GTMDI_ATOM_WPC2_SEN1_SHIFT (16U) 588 #define GTMDI_ATOM_WPC2_SEN1_WIDTH (1U) 589 #define GTMDI_ATOM_WPC2_SEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ATOM_WPC2_SEN1_SHIFT)) & GTMDI_ATOM_WPC2_SEN1_MASK) 590 591 #define GTMDI_ATOM_WPC2_TEN1_MASK (0x20000U) 592 #define GTMDI_ATOM_WPC2_TEN1_SHIFT (17U) 593 #define GTMDI_ATOM_WPC2_TEN1_WIDTH (1U) 594 #define GTMDI_ATOM_WPC2_TEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ATOM_WPC2_TEN1_SHIFT)) & GTMDI_ATOM_WPC2_TEN1_MASK) 595 596 #define GTMDI_ATOM_WPC2_STSEL1_MASK (0x300000U) 597 #define GTMDI_ATOM_WPC2_STSEL1_SHIFT (20U) 598 #define GTMDI_ATOM_WPC2_STSEL1_WIDTH (2U) 599 #define GTMDI_ATOM_WPC2_STSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ATOM_WPC2_STSEL1_SHIFT)) & GTMDI_ATOM_WPC2_STSEL1_MASK) 600 601 #define GTMDI_ATOM_WPC2_WTSEL1_MASK (0x70000000U) 602 #define GTMDI_ATOM_WPC2_WTSEL1_SHIFT (28U) 603 #define GTMDI_ATOM_WPC2_WTSEL1_WIDTH (3U) 604 #define GTMDI_ATOM_WPC2_WTSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ATOM_WPC2_WTSEL1_SHIFT)) & GTMDI_ATOM_WPC2_WTSEL1_MASK) 605 /*! @} */ 606 607 /*! @name SPEA_WPC1 - SPEA Watchpoint Control 1 */ 608 /*! @{ */ 609 610 #define GTMDI_SPEA_WPC1_HEN2_MASK (0x2U) 611 #define GTMDI_SPEA_WPC1_HEN2_SHIFT (1U) 612 #define GTMDI_SPEA_WPC1_HEN2_WIDTH (1U) 613 #define GTMDI_SPEA_WPC1_HEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEA_WPC1_HEN2_SHIFT)) & GTMDI_SPEA_WPC1_HEN2_MASK) 614 615 #define GTMDI_SPEA_WPC1_TSS2_MASK (0x30U) 616 #define GTMDI_SPEA_WPC1_TSS2_SHIFT (4U) 617 #define GTMDI_SPEA_WPC1_TSS2_WIDTH (2U) 618 #define GTMDI_SPEA_WPC1_TSS2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEA_WPC1_TSS2_SHIFT)) & GTMDI_SPEA_WPC1_TSS2_MASK) 619 620 #define GTMDI_SPEA_WPC1_WMC2_MASK (0x40U) 621 #define GTMDI_SPEA_WPC1_WMC2_SHIFT (6U) 622 #define GTMDI_SPEA_WPC1_WMC2_WIDTH (1U) 623 #define GTMDI_SPEA_WPC1_WMC2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEA_WPC1_WMC2_SHIFT)) & GTMDI_SPEA_WPC1_WMC2_MASK) 624 625 #define GTMDI_SPEA_WPC1_HEN1_MASK (0x20000U) 626 #define GTMDI_SPEA_WPC1_HEN1_SHIFT (17U) 627 #define GTMDI_SPEA_WPC1_HEN1_WIDTH (1U) 628 #define GTMDI_SPEA_WPC1_HEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEA_WPC1_HEN1_SHIFT)) & GTMDI_SPEA_WPC1_HEN1_MASK) 629 630 #define GTMDI_SPEA_WPC1_TSS1_MASK (0x300000U) 631 #define GTMDI_SPEA_WPC1_TSS1_SHIFT (20U) 632 #define GTMDI_SPEA_WPC1_TSS1_WIDTH (2U) 633 #define GTMDI_SPEA_WPC1_TSS1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEA_WPC1_TSS1_SHIFT)) & GTMDI_SPEA_WPC1_TSS1_MASK) 634 635 #define GTMDI_SPEA_WPC1_WMC1_MASK (0x400000U) 636 #define GTMDI_SPEA_WPC1_WMC1_SHIFT (22U) 637 #define GTMDI_SPEA_WPC1_WMC1_WIDTH (1U) 638 #define GTMDI_SPEA_WPC1_WMC1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEA_WPC1_WMC1_SHIFT)) & GTMDI_SPEA_WPC1_WMC1_MASK) 639 640 #define GTMDI_SPEA_WPC1_SSEL_MASK (0x7000000U) 641 #define GTMDI_SPEA_WPC1_SSEL_SHIFT (24U) 642 #define GTMDI_SPEA_WPC1_SSEL_WIDTH (3U) 643 #define GTMDI_SPEA_WPC1_SSEL(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEA_WPC1_SSEL_SHIFT)) & GTMDI_SPEA_WPC1_SSEL_MASK) 644 /*! @} */ 645 646 /*! @name SPEA_WPC2 - SPEA Watchpoint Control 2 */ 647 /*! @{ */ 648 649 #define GTMDI_SPEA_WPC2_SEN2_MASK (0x1U) 650 #define GTMDI_SPEA_WPC2_SEN2_SHIFT (0U) 651 #define GTMDI_SPEA_WPC2_SEN2_WIDTH (1U) 652 #define GTMDI_SPEA_WPC2_SEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEA_WPC2_SEN2_SHIFT)) & GTMDI_SPEA_WPC2_SEN2_MASK) 653 654 #define GTMDI_SPEA_WPC2_TEN2_MASK (0x2U) 655 #define GTMDI_SPEA_WPC2_TEN2_SHIFT (1U) 656 #define GTMDI_SPEA_WPC2_TEN2_WIDTH (1U) 657 #define GTMDI_SPEA_WPC2_TEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEA_WPC2_TEN2_SHIFT)) & GTMDI_SPEA_WPC2_TEN2_MASK) 658 659 #define GTMDI_SPEA_WPC2_STSEL2_MASK (0x30U) 660 #define GTMDI_SPEA_WPC2_STSEL2_SHIFT (4U) 661 #define GTMDI_SPEA_WPC2_STSEL2_WIDTH (2U) 662 #define GTMDI_SPEA_WPC2_STSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEA_WPC2_STSEL2_SHIFT)) & GTMDI_SPEA_WPC2_STSEL2_MASK) 663 664 #define GTMDI_SPEA_WPC2_WTSEL2_MASK (0x7000U) 665 #define GTMDI_SPEA_WPC2_WTSEL2_SHIFT (12U) 666 #define GTMDI_SPEA_WPC2_WTSEL2_WIDTH (3U) 667 #define GTMDI_SPEA_WPC2_WTSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEA_WPC2_WTSEL2_SHIFT)) & GTMDI_SPEA_WPC2_WTSEL2_MASK) 668 669 #define GTMDI_SPEA_WPC2_SEN1_MASK (0x10000U) 670 #define GTMDI_SPEA_WPC2_SEN1_SHIFT (16U) 671 #define GTMDI_SPEA_WPC2_SEN1_WIDTH (1U) 672 #define GTMDI_SPEA_WPC2_SEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEA_WPC2_SEN1_SHIFT)) & GTMDI_SPEA_WPC2_SEN1_MASK) 673 674 #define GTMDI_SPEA_WPC2_TEN1_MASK (0x20000U) 675 #define GTMDI_SPEA_WPC2_TEN1_SHIFT (17U) 676 #define GTMDI_SPEA_WPC2_TEN1_WIDTH (1U) 677 #define GTMDI_SPEA_WPC2_TEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEA_WPC2_TEN1_SHIFT)) & GTMDI_SPEA_WPC2_TEN1_MASK) 678 679 #define GTMDI_SPEA_WPC2_STSEL1_MASK (0x300000U) 680 #define GTMDI_SPEA_WPC2_STSEL1_SHIFT (20U) 681 #define GTMDI_SPEA_WPC2_STSEL1_WIDTH (2U) 682 #define GTMDI_SPEA_WPC2_STSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEA_WPC2_STSEL1_SHIFT)) & GTMDI_SPEA_WPC2_STSEL1_MASK) 683 684 #define GTMDI_SPEA_WPC2_WTSEL1_MASK (0x70000000U) 685 #define GTMDI_SPEA_WPC2_WTSEL1_SHIFT (28U) 686 #define GTMDI_SPEA_WPC2_WTSEL1_WIDTH (3U) 687 #define GTMDI_SPEA_WPC2_WTSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEA_WPC2_WTSEL1_SHIFT)) & GTMDI_SPEA_WPC2_WTSEL1_MASK) 688 /*! @} */ 689 690 /*! @name SPEB_WPC1 - SPEB Watchpoint Control 1 */ 691 /*! @{ */ 692 693 #define GTMDI_SPEB_WPC1_HEN2_MASK (0x2U) 694 #define GTMDI_SPEB_WPC1_HEN2_SHIFT (1U) 695 #define GTMDI_SPEB_WPC1_HEN2_WIDTH (1U) 696 #define GTMDI_SPEB_WPC1_HEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEB_WPC1_HEN2_SHIFT)) & GTMDI_SPEB_WPC1_HEN2_MASK) 697 698 #define GTMDI_SPEB_WPC1_TSS2_MASK (0x30U) 699 #define GTMDI_SPEB_WPC1_TSS2_SHIFT (4U) 700 #define GTMDI_SPEB_WPC1_TSS2_WIDTH (2U) 701 #define GTMDI_SPEB_WPC1_TSS2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEB_WPC1_TSS2_SHIFT)) & GTMDI_SPEB_WPC1_TSS2_MASK) 702 703 #define GTMDI_SPEB_WPC1_WMC2_MASK (0x40U) 704 #define GTMDI_SPEB_WPC1_WMC2_SHIFT (6U) 705 #define GTMDI_SPEB_WPC1_WMC2_WIDTH (1U) 706 #define GTMDI_SPEB_WPC1_WMC2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEB_WPC1_WMC2_SHIFT)) & GTMDI_SPEB_WPC1_WMC2_MASK) 707 708 #define GTMDI_SPEB_WPC1_HEN1_MASK (0x20000U) 709 #define GTMDI_SPEB_WPC1_HEN1_SHIFT (17U) 710 #define GTMDI_SPEB_WPC1_HEN1_WIDTH (1U) 711 #define GTMDI_SPEB_WPC1_HEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEB_WPC1_HEN1_SHIFT)) & GTMDI_SPEB_WPC1_HEN1_MASK) 712 713 #define GTMDI_SPEB_WPC1_TSS1_MASK (0x300000U) 714 #define GTMDI_SPEB_WPC1_TSS1_SHIFT (20U) 715 #define GTMDI_SPEB_WPC1_TSS1_WIDTH (2U) 716 #define GTMDI_SPEB_WPC1_TSS1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEB_WPC1_TSS1_SHIFT)) & GTMDI_SPEB_WPC1_TSS1_MASK) 717 718 #define GTMDI_SPEB_WPC1_WMC1_MASK (0x400000U) 719 #define GTMDI_SPEB_WPC1_WMC1_SHIFT (22U) 720 #define GTMDI_SPEB_WPC1_WMC1_WIDTH (1U) 721 #define GTMDI_SPEB_WPC1_WMC1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEB_WPC1_WMC1_SHIFT)) & GTMDI_SPEB_WPC1_WMC1_MASK) 722 723 #define GTMDI_SPEB_WPC1_SSEL_MASK (0x7000000U) 724 #define GTMDI_SPEB_WPC1_SSEL_SHIFT (24U) 725 #define GTMDI_SPEB_WPC1_SSEL_WIDTH (3U) 726 #define GTMDI_SPEB_WPC1_SSEL(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEB_WPC1_SSEL_SHIFT)) & GTMDI_SPEB_WPC1_SSEL_MASK) 727 /*! @} */ 728 729 /*! @name SPEB_WPC2 - SPEB Watchpoint Control 2 */ 730 /*! @{ */ 731 732 #define GTMDI_SPEB_WPC2_SEN2_MASK (0x1U) 733 #define GTMDI_SPEB_WPC2_SEN2_SHIFT (0U) 734 #define GTMDI_SPEB_WPC2_SEN2_WIDTH (1U) 735 #define GTMDI_SPEB_WPC2_SEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEB_WPC2_SEN2_SHIFT)) & GTMDI_SPEB_WPC2_SEN2_MASK) 736 737 #define GTMDI_SPEB_WPC2_TEN2_MASK (0x2U) 738 #define GTMDI_SPEB_WPC2_TEN2_SHIFT (1U) 739 #define GTMDI_SPEB_WPC2_TEN2_WIDTH (1U) 740 #define GTMDI_SPEB_WPC2_TEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEB_WPC2_TEN2_SHIFT)) & GTMDI_SPEB_WPC2_TEN2_MASK) 741 742 #define GTMDI_SPEB_WPC2_STSEL2_MASK (0x30U) 743 #define GTMDI_SPEB_WPC2_STSEL2_SHIFT (4U) 744 #define GTMDI_SPEB_WPC2_STSEL2_WIDTH (2U) 745 #define GTMDI_SPEB_WPC2_STSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEB_WPC2_STSEL2_SHIFT)) & GTMDI_SPEB_WPC2_STSEL2_MASK) 746 747 #define GTMDI_SPEB_WPC2_WTSEL2_MASK (0x7000U) 748 #define GTMDI_SPEB_WPC2_WTSEL2_SHIFT (12U) 749 #define GTMDI_SPEB_WPC2_WTSEL2_WIDTH (3U) 750 #define GTMDI_SPEB_WPC2_WTSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEB_WPC2_WTSEL2_SHIFT)) & GTMDI_SPEB_WPC2_WTSEL2_MASK) 751 752 #define GTMDI_SPEB_WPC2_SEN1_MASK (0x10000U) 753 #define GTMDI_SPEB_WPC2_SEN1_SHIFT (16U) 754 #define GTMDI_SPEB_WPC2_SEN1_WIDTH (1U) 755 #define GTMDI_SPEB_WPC2_SEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEB_WPC2_SEN1_SHIFT)) & GTMDI_SPEB_WPC2_SEN1_MASK) 756 757 #define GTMDI_SPEB_WPC2_TEN1_MASK (0x20000U) 758 #define GTMDI_SPEB_WPC2_TEN1_SHIFT (17U) 759 #define GTMDI_SPEB_WPC2_TEN1_WIDTH (1U) 760 #define GTMDI_SPEB_WPC2_TEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEB_WPC2_TEN1_SHIFT)) & GTMDI_SPEB_WPC2_TEN1_MASK) 761 762 #define GTMDI_SPEB_WPC2_STSEL1_MASK (0x300000U) 763 #define GTMDI_SPEB_WPC2_STSEL1_SHIFT (20U) 764 #define GTMDI_SPEB_WPC2_STSEL1_WIDTH (2U) 765 #define GTMDI_SPEB_WPC2_STSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEB_WPC2_STSEL1_SHIFT)) & GTMDI_SPEB_WPC2_STSEL1_MASK) 766 767 #define GTMDI_SPEB_WPC2_WTSEL1_MASK (0x70000000U) 768 #define GTMDI_SPEB_WPC2_WTSEL1_SHIFT (28U) 769 #define GTMDI_SPEB_WPC2_WTSEL1_WIDTH (3U) 770 #define GTMDI_SPEB_WPC2_WTSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_SPEB_WPC2_WTSEL1_SHIFT)) & GTMDI_SPEB_WPC2_WTSEL1_MASK) 771 /*! @} */ 772 773 /*! @name DPLL_WPC1 - DPLL Watchpoint Control 1 */ 774 /*! @{ */ 775 776 #define GTMDI_DPLL_WPC1_HEN2_MASK (0x2U) 777 #define GTMDI_DPLL_WPC1_HEN2_SHIFT (1U) 778 #define GTMDI_DPLL_WPC1_HEN2_WIDTH (1U) 779 #define GTMDI_DPLL_WPC1_HEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_WPC1_HEN2_SHIFT)) & GTMDI_DPLL_WPC1_HEN2_MASK) 780 781 #define GTMDI_DPLL_WPC1_WMC2_MASK (0x40U) 782 #define GTMDI_DPLL_WPC1_WMC2_SHIFT (6U) 783 #define GTMDI_DPLL_WPC1_WMC2_WIDTH (1U) 784 #define GTMDI_DPLL_WPC1_WMC2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_WPC1_WMC2_SHIFT)) & GTMDI_DPLL_WPC1_WMC2_MASK) 785 786 #define GTMDI_DPLL_WPC1_TSEL2A_MASK (0x300U) 787 #define GTMDI_DPLL_WPC1_TSEL2A_SHIFT (8U) 788 #define GTMDI_DPLL_WPC1_TSEL2A_WIDTH (2U) 789 #define GTMDI_DPLL_WPC1_TSEL2A(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_WPC1_TSEL2A_SHIFT)) & GTMDI_DPLL_WPC1_TSEL2A_MASK) 790 791 #define GTMDI_DPLL_WPC1_TSEL2B_MASK (0x3000U) 792 #define GTMDI_DPLL_WPC1_TSEL2B_SHIFT (12U) 793 #define GTMDI_DPLL_WPC1_TSEL2B_WIDTH (2U) 794 #define GTMDI_DPLL_WPC1_TSEL2B(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_WPC1_TSEL2B_SHIFT)) & GTMDI_DPLL_WPC1_TSEL2B_MASK) 795 796 #define GTMDI_DPLL_WPC1_HEN1_MASK (0x20000U) 797 #define GTMDI_DPLL_WPC1_HEN1_SHIFT (17U) 798 #define GTMDI_DPLL_WPC1_HEN1_WIDTH (1U) 799 #define GTMDI_DPLL_WPC1_HEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_WPC1_HEN1_SHIFT)) & GTMDI_DPLL_WPC1_HEN1_MASK) 800 801 #define GTMDI_DPLL_WPC1_TSS1_MASK (0x300000U) 802 #define GTMDI_DPLL_WPC1_TSS1_SHIFT (20U) 803 #define GTMDI_DPLL_WPC1_TSS1_WIDTH (2U) 804 #define GTMDI_DPLL_WPC1_TSS1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_WPC1_TSS1_SHIFT)) & GTMDI_DPLL_WPC1_TSS1_MASK) 805 806 #define GTMDI_DPLL_WPC1_WMC1_MASK (0x400000U) 807 #define GTMDI_DPLL_WPC1_WMC1_SHIFT (22U) 808 #define GTMDI_DPLL_WPC1_WMC1_WIDTH (1U) 809 #define GTMDI_DPLL_WPC1_WMC1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_WPC1_WMC1_SHIFT)) & GTMDI_DPLL_WPC1_WMC1_MASK) 810 811 #define GTMDI_DPLL_WPC1_TSEL1_MASK (0x3000000U) 812 #define GTMDI_DPLL_WPC1_TSEL1_SHIFT (24U) 813 #define GTMDI_DPLL_WPC1_TSEL1_WIDTH (2U) 814 #define GTMDI_DPLL_WPC1_TSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_WPC1_TSEL1_SHIFT)) & GTMDI_DPLL_WPC1_TSEL1_MASK) 815 /*! @} */ 816 817 /*! @name DPLL_WPC2 - DPLL Watchpoint Control 2 */ 818 /*! @{ */ 819 820 #define GTMDI_DPLL_WPC2_SEN2_MASK (0x1U) 821 #define GTMDI_DPLL_WPC2_SEN2_SHIFT (0U) 822 #define GTMDI_DPLL_WPC2_SEN2_WIDTH (1U) 823 #define GTMDI_DPLL_WPC2_SEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_WPC2_SEN2_SHIFT)) & GTMDI_DPLL_WPC2_SEN2_MASK) 824 825 #define GTMDI_DPLL_WPC2_TEN2_MASK (0x2U) 826 #define GTMDI_DPLL_WPC2_TEN2_SHIFT (1U) 827 #define GTMDI_DPLL_WPC2_TEN2_WIDTH (1U) 828 #define GTMDI_DPLL_WPC2_TEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_WPC2_TEN2_SHIFT)) & GTMDI_DPLL_WPC2_TEN2_MASK) 829 830 #define GTMDI_DPLL_WPC2_STSEL2_MASK (0x30U) 831 #define GTMDI_DPLL_WPC2_STSEL2_SHIFT (4U) 832 #define GTMDI_DPLL_WPC2_STSEL2_WIDTH (2U) 833 #define GTMDI_DPLL_WPC2_STSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_WPC2_STSEL2_SHIFT)) & GTMDI_DPLL_WPC2_STSEL2_MASK) 834 835 #define GTMDI_DPLL_WPC2_WTSEL2_MASK (0x7000U) 836 #define GTMDI_DPLL_WPC2_WTSEL2_SHIFT (12U) 837 #define GTMDI_DPLL_WPC2_WTSEL2_WIDTH (3U) 838 #define GTMDI_DPLL_WPC2_WTSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_WPC2_WTSEL2_SHIFT)) & GTMDI_DPLL_WPC2_WTSEL2_MASK) 839 840 #define GTMDI_DPLL_WPC2_SEN1_MASK (0x10000U) 841 #define GTMDI_DPLL_WPC2_SEN1_SHIFT (16U) 842 #define GTMDI_DPLL_WPC2_SEN1_WIDTH (1U) 843 #define GTMDI_DPLL_WPC2_SEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_WPC2_SEN1_SHIFT)) & GTMDI_DPLL_WPC2_SEN1_MASK) 844 845 #define GTMDI_DPLL_WPC2_TEN1_MASK (0x20000U) 846 #define GTMDI_DPLL_WPC2_TEN1_SHIFT (17U) 847 #define GTMDI_DPLL_WPC2_TEN1_WIDTH (1U) 848 #define GTMDI_DPLL_WPC2_TEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_WPC2_TEN1_SHIFT)) & GTMDI_DPLL_WPC2_TEN1_MASK) 849 850 #define GTMDI_DPLL_WPC2_STSEL1_MASK (0x300000U) 851 #define GTMDI_DPLL_WPC2_STSEL1_SHIFT (20U) 852 #define GTMDI_DPLL_WPC2_STSEL1_WIDTH (2U) 853 #define GTMDI_DPLL_WPC2_STSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_WPC2_STSEL1_SHIFT)) & GTMDI_DPLL_WPC2_STSEL1_MASK) 854 855 #define GTMDI_DPLL_WPC2_WTSEL1_MASK (0x70000000U) 856 #define GTMDI_DPLL_WPC2_WTSEL1_SHIFT (28U) 857 #define GTMDI_DPLL_WPC2_WTSEL1_WIDTH (3U) 858 #define GTMDI_DPLL_WPC2_WTSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_WPC2_WTSEL1_SHIFT)) & GTMDI_DPLL_WPC2_WTSEL1_MASK) 859 /*! @} */ 860 861 /*! @name DPLL_WPC3 - DPLL Watchpoint Control 3 */ 862 /*! @{ */ 863 864 #define GTMDI_DPLL_WPC3_RAM_DATA_MASK (0xFFFFFFU) 865 #define GTMDI_DPLL_WPC3_RAM_DATA_SHIFT (0U) 866 #define GTMDI_DPLL_WPC3_RAM_DATA_WIDTH (24U) 867 #define GTMDI_DPLL_WPC3_RAM_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_WPC3_RAM_DATA_SHIFT)) & GTMDI_DPLL_WPC3_RAM_DATA_MASK) 868 869 #define GTMDI_DPLL_WPC3_DMASK_MASK (0x10000000U) 870 #define GTMDI_DPLL_WPC3_DMASK_SHIFT (28U) 871 #define GTMDI_DPLL_WPC3_DMASK_WIDTH (1U) 872 #define GTMDI_DPLL_WPC3_DMASK(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_WPC3_DMASK_SHIFT)) & GTMDI_DPLL_WPC3_DMASK_MASK) 873 /*! @} */ 874 875 /*! @name DPLL_WPC4 - DPLL Watchpoint Control 4 */ 876 /*! @{ */ 877 878 #define GTMDI_DPLL_WPC4_RAM_ADDR_MASK_MASK (0xFFFU) 879 #define GTMDI_DPLL_WPC4_RAM_ADDR_MASK_SHIFT (0U) 880 #define GTMDI_DPLL_WPC4_RAM_ADDR_MASK_WIDTH (12U) 881 #define GTMDI_DPLL_WPC4_RAM_ADDR_MASK(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_WPC4_RAM_ADDR_MASK_SHIFT)) & GTMDI_DPLL_WPC4_RAM_ADDR_MASK_MASK) 882 /*! @} */ 883 884 /*! @name DPLL_WPC5 - DPLL Watchpoint Control 5 */ 885 /*! @{ */ 886 887 #define GTMDI_DPLL_WPC5_RAM_ADDR_MASK (0xFFFU) 888 #define GTMDI_DPLL_WPC5_RAM_ADDR_SHIFT (0U) 889 #define GTMDI_DPLL_WPC5_RAM_ADDR_WIDTH (12U) 890 #define GTMDI_DPLL_WPC5_RAM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_WPC5_RAM_ADDR_SHIFT)) & GTMDI_DPLL_WPC5_RAM_ADDR_MASK) 891 /*! @} */ 892 893 /*! @name DPLL_DTC - DPLL Data Trace Control */ 894 /*! @{ */ 895 896 #define GTMDI_DPLL_DTC_SEN_MASK (0x1U) 897 #define GTMDI_DPLL_DTC_SEN_SHIFT (0U) 898 #define GTMDI_DPLL_DTC_SEN_WIDTH (1U) 899 #define GTMDI_DPLL_DTC_SEN(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_DTC_SEN_SHIFT)) & GTMDI_DPLL_DTC_SEN_MASK) 900 901 #define GTMDI_DPLL_DTC_STSEL_MASK (0x30U) 902 #define GTMDI_DPLL_DTC_STSEL_SHIFT (4U) 903 #define GTMDI_DPLL_DTC_STSEL_WIDTH (2U) 904 #define GTMDI_DPLL_DTC_STSEL(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_DTC_STSEL_SHIFT)) & GTMDI_DPLL_DTC_STSEL_MASK) 905 906 #define GTMDI_DPLL_DTC_DMC_MASK (0x40U) 907 #define GTMDI_DPLL_DTC_DMC_SHIFT (6U) 908 #define GTMDI_DPLL_DTC_DMC_WIDTH (1U) 909 #define GTMDI_DPLL_DTC_DMC(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_DTC_DMC_SHIFT)) & GTMDI_DPLL_DTC_DMC_MASK) 910 911 #define GTMDI_DPLL_DTC_RAMSEL_MASK (0x300U) 912 #define GTMDI_DPLL_DTC_RAMSEL_SHIFT (8U) 913 #define GTMDI_DPLL_DTC_RAMSEL_WIDTH (2U) 914 #define GTMDI_DPLL_DTC_RAMSEL(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_DTC_RAMSEL_SHIFT)) & GTMDI_DPLL_DTC_RAMSEL_MASK) 915 916 #define GTMDI_DPLL_DTC_RWC_MASK (0x3000U) 917 #define GTMDI_DPLL_DTC_RWC_SHIFT (12U) 918 #define GTMDI_DPLL_DTC_RWC_WIDTH (2U) 919 #define GTMDI_DPLL_DTC_RWC(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DPLL_DTC_RWC_SHIFT)) & GTMDI_DPLL_DTC_RWC_MASK) 920 /*! @} */ 921 922 /*! @name ARU_WPC1 - ARU Watchpoint Control 1 */ 923 /*! @{ */ 924 925 #define GTMDI_ARU_WPC1_WMC2_MASK (0x40U) 926 #define GTMDI_ARU_WPC1_WMC2_SHIFT (6U) 927 #define GTMDI_ARU_WPC1_WMC2_WIDTH (1U) 928 #define GTMDI_ARU_WPC1_WMC2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_WPC1_WMC2_SHIFT)) & GTMDI_ARU_WPC1_WMC2_MASK) 929 930 #define GTMDI_ARU_WPC1_HEN2_MASK (0x80U) 931 #define GTMDI_ARU_WPC1_HEN2_SHIFT (7U) 932 #define GTMDI_ARU_WPC1_HEN2_WIDTH (1U) 933 #define GTMDI_ARU_WPC1_HEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_WPC1_HEN2_SHIFT)) & GTMDI_ARU_WPC1_HEN2_MASK) 934 935 #define GTMDI_ARU_WPC1_TSS2_MASK (0x1000U) 936 #define GTMDI_ARU_WPC1_TSS2_SHIFT (12U) 937 #define GTMDI_ARU_WPC1_TSS2_WIDTH (1U) 938 #define GTMDI_ARU_WPC1_TSS2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_WPC1_TSS2_SHIFT)) & GTMDI_ARU_WPC1_TSS2_MASK) 939 940 #define GTMDI_ARU_WPC1_WMC1_MASK (0x400000U) 941 #define GTMDI_ARU_WPC1_WMC1_SHIFT (22U) 942 #define GTMDI_ARU_WPC1_WMC1_WIDTH (1U) 943 #define GTMDI_ARU_WPC1_WMC1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_WPC1_WMC1_SHIFT)) & GTMDI_ARU_WPC1_WMC1_MASK) 944 945 #define GTMDI_ARU_WPC1_HEN1_MASK (0x800000U) 946 #define GTMDI_ARU_WPC1_HEN1_SHIFT (23U) 947 #define GTMDI_ARU_WPC1_HEN1_WIDTH (1U) 948 #define GTMDI_ARU_WPC1_HEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_WPC1_HEN1_SHIFT)) & GTMDI_ARU_WPC1_HEN1_MASK) 949 950 #define GTMDI_ARU_WPC1_TSS1_MASK (0x10000000U) 951 #define GTMDI_ARU_WPC1_TSS1_SHIFT (28U) 952 #define GTMDI_ARU_WPC1_TSS1_WIDTH (1U) 953 #define GTMDI_ARU_WPC1_TSS1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_WPC1_TSS1_SHIFT)) & GTMDI_ARU_WPC1_TSS1_MASK) 954 /*! @} */ 955 956 /*! @name ARU_WPC2 - ARU Watchpoint Control 2 */ 957 /*! @{ */ 958 959 #define GTMDI_ARU_WPC2_SEN2_MASK (0x1U) 960 #define GTMDI_ARU_WPC2_SEN2_SHIFT (0U) 961 #define GTMDI_ARU_WPC2_SEN2_WIDTH (1U) 962 #define GTMDI_ARU_WPC2_SEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_WPC2_SEN2_SHIFT)) & GTMDI_ARU_WPC2_SEN2_MASK) 963 964 #define GTMDI_ARU_WPC2_TEN2_MASK (0x2U) 965 #define GTMDI_ARU_WPC2_TEN2_SHIFT (1U) 966 #define GTMDI_ARU_WPC2_TEN2_WIDTH (1U) 967 #define GTMDI_ARU_WPC2_TEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_WPC2_TEN2_SHIFT)) & GTMDI_ARU_WPC2_TEN2_MASK) 968 969 #define GTMDI_ARU_WPC2_STSEL2_MASK (0x30U) 970 #define GTMDI_ARU_WPC2_STSEL2_SHIFT (4U) 971 #define GTMDI_ARU_WPC2_STSEL2_WIDTH (2U) 972 #define GTMDI_ARU_WPC2_STSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_WPC2_STSEL2_SHIFT)) & GTMDI_ARU_WPC2_STSEL2_MASK) 973 974 #define GTMDI_ARU_WPC2_WTSEL2_MASK (0x7000U) 975 #define GTMDI_ARU_WPC2_WTSEL2_SHIFT (12U) 976 #define GTMDI_ARU_WPC2_WTSEL2_WIDTH (3U) 977 #define GTMDI_ARU_WPC2_WTSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_WPC2_WTSEL2_SHIFT)) & GTMDI_ARU_WPC2_WTSEL2_MASK) 978 979 #define GTMDI_ARU_WPC2_SEN1_MASK (0x10000U) 980 #define GTMDI_ARU_WPC2_SEN1_SHIFT (16U) 981 #define GTMDI_ARU_WPC2_SEN1_WIDTH (1U) 982 #define GTMDI_ARU_WPC2_SEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_WPC2_SEN1_SHIFT)) & GTMDI_ARU_WPC2_SEN1_MASK) 983 984 #define GTMDI_ARU_WPC2_TEN1_MASK (0x20000U) 985 #define GTMDI_ARU_WPC2_TEN1_SHIFT (17U) 986 #define GTMDI_ARU_WPC2_TEN1_WIDTH (1U) 987 #define GTMDI_ARU_WPC2_TEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_WPC2_TEN1_SHIFT)) & GTMDI_ARU_WPC2_TEN1_MASK) 988 989 #define GTMDI_ARU_WPC2_STSEL1_MASK (0x300000U) 990 #define GTMDI_ARU_WPC2_STSEL1_SHIFT (20U) 991 #define GTMDI_ARU_WPC2_STSEL1_WIDTH (2U) 992 #define GTMDI_ARU_WPC2_STSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_WPC2_STSEL1_SHIFT)) & GTMDI_ARU_WPC2_STSEL1_MASK) 993 994 #define GTMDI_ARU_WPC2_WTSEL1_MASK (0x70000000U) 995 #define GTMDI_ARU_WPC2_WTSEL1_SHIFT (28U) 996 #define GTMDI_ARU_WPC2_WTSEL1_WIDTH (3U) 997 #define GTMDI_ARU_WPC2_WTSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_WPC2_WTSEL1_SHIFT)) & GTMDI_ARU_WPC2_WTSEL1_MASK) 998 /*! @} */ 999 1000 /*! @name ARU_D0H - ARU Watchpoint DATA0H */ 1001 /*! @{ */ 1002 1003 #define GTMDI_ARU_D0H_DATA0H_MASK (0x1FFFFFFFU) 1004 #define GTMDI_ARU_D0H_DATA0H_SHIFT (0U) 1005 #define GTMDI_ARU_D0H_DATA0H_WIDTH (29U) 1006 #define GTMDI_ARU_D0H_DATA0H(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_D0H_DATA0H_SHIFT)) & GTMDI_ARU_D0H_DATA0H_MASK) 1007 /*! @} */ 1008 1009 /*! @name ARU_D0L - ARU Watchpoint DATA0L */ 1010 /*! @{ */ 1011 1012 #define GTMDI_ARU_D0L_DATA0L_MASK (0x1FFFFFFFU) 1013 #define GTMDI_ARU_D0L_DATA0L_SHIFT (0U) 1014 #define GTMDI_ARU_D0L_DATA0L_WIDTH (29U) 1015 #define GTMDI_ARU_D0L_DATA0L(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_D0L_DATA0L_SHIFT)) & GTMDI_ARU_D0L_DATA0L_MASK) 1016 /*! @} */ 1017 1018 /*! @name ARU_D1H - ARU Watchpoint DATA1H */ 1019 /*! @{ */ 1020 1021 #define GTMDI_ARU_D1H_DATA1H_MASK (0x1FFFFFFFU) 1022 #define GTMDI_ARU_D1H_DATA1H_SHIFT (0U) 1023 #define GTMDI_ARU_D1H_DATA1H_WIDTH (29U) 1024 #define GTMDI_ARU_D1H_DATA1H(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_D1H_DATA1H_SHIFT)) & GTMDI_ARU_D1H_DATA1H_MASK) 1025 /*! @} */ 1026 1027 /*! @name ARU_D1L - ARU Watchpoint ARUD1L */ 1028 /*! @{ */ 1029 1030 #define GTMDI_ARU_D1L_DATA1L_MASK (0x1FFFFFFFU) 1031 #define GTMDI_ARU_D1L_DATA1L_SHIFT (0U) 1032 #define GTMDI_ARU_D1L_DATA1L_WIDTH (29U) 1033 #define GTMDI_ARU_D1L_DATA1L(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_D1L_DATA1L_SHIFT)) & GTMDI_ARU_D1L_DATA1L_MASK) 1034 /*! @} */ 1035 1036 /*! @name ARU_DTC - ARU Data Trace Control */ 1037 /*! @{ */ 1038 1039 #define GTMDI_ARU_DTC_SEN2_MASK (0x1U) 1040 #define GTMDI_ARU_DTC_SEN2_SHIFT (0U) 1041 #define GTMDI_ARU_DTC_SEN2_WIDTH (1U) 1042 #define GTMDI_ARU_DTC_SEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_DTC_SEN2_SHIFT)) & GTMDI_ARU_DTC_SEN2_MASK) 1043 1044 #define GTMDI_ARU_DTC_DMC2_MASK (0x2U) 1045 #define GTMDI_ARU_DTC_DMC2_SHIFT (1U) 1046 #define GTMDI_ARU_DTC_DMC2_WIDTH (1U) 1047 #define GTMDI_ARU_DTC_DMC2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_DTC_DMC2_SHIFT)) & GTMDI_ARU_DTC_DMC2_MASK) 1048 1049 #define GTMDI_ARU_DTC_STSEL2_MASK (0x30U) 1050 #define GTMDI_ARU_DTC_STSEL2_SHIFT (4U) 1051 #define GTMDI_ARU_DTC_STSEL2_WIDTH (2U) 1052 #define GTMDI_ARU_DTC_STSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_DTC_STSEL2_SHIFT)) & GTMDI_ARU_DTC_STSEL2_MASK) 1053 1054 #define GTMDI_ARU_DTC_SEN1_MASK (0x10000U) 1055 #define GTMDI_ARU_DTC_SEN1_SHIFT (16U) 1056 #define GTMDI_ARU_DTC_SEN1_WIDTH (1U) 1057 #define GTMDI_ARU_DTC_SEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_DTC_SEN1_SHIFT)) & GTMDI_ARU_DTC_SEN1_MASK) 1058 1059 #define GTMDI_ARU_DTC_DMC1_MASK (0x20000U) 1060 #define GTMDI_ARU_DTC_DMC1_SHIFT (17U) 1061 #define GTMDI_ARU_DTC_DMC1_WIDTH (1U) 1062 #define GTMDI_ARU_DTC_DMC1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_DTC_DMC1_SHIFT)) & GTMDI_ARU_DTC_DMC1_MASK) 1063 1064 #define GTMDI_ARU_DTC_STSEL1_MASK (0x300000U) 1065 #define GTMDI_ARU_DTC_STSEL1_SHIFT (20U) 1066 #define GTMDI_ARU_DTC_STSEL1_WIDTH (2U) 1067 #define GTMDI_ARU_DTC_STSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ARU_DTC_STSEL1_SHIFT)) & GTMDI_ARU_DTC_STSEL1_MASK) 1068 /*! @} */ 1069 1070 /*! @name MCS_HBC - MCS Hardware Breakpoint (HBP) Control */ 1071 /*! @{ */ 1072 1073 #define GTMDI_MCS_HBC_MCS0BE_MASK (0x1U) 1074 #define GTMDI_MCS_HBC_MCS0BE_SHIFT (0U) 1075 #define GTMDI_MCS_HBC_MCS0BE_WIDTH (1U) 1076 #define GTMDI_MCS_HBC_MCS0BE(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCS_HBC_MCS0BE_SHIFT)) & GTMDI_MCS_HBC_MCS0BE_MASK) 1077 1078 #define GTMDI_MCS_HBC_MCS1BE_MASK (0x2U) 1079 #define GTMDI_MCS_HBC_MCS1BE_SHIFT (1U) 1080 #define GTMDI_MCS_HBC_MCS1BE_WIDTH (1U) 1081 #define GTMDI_MCS_HBC_MCS1BE(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCS_HBC_MCS1BE_SHIFT)) & GTMDI_MCS_HBC_MCS1BE_MASK) 1082 1083 #define GTMDI_MCS_HBC_MCS2BE_MASK (0x4U) 1084 #define GTMDI_MCS_HBC_MCS2BE_SHIFT (2U) 1085 #define GTMDI_MCS_HBC_MCS2BE_WIDTH (1U) 1086 #define GTMDI_MCS_HBC_MCS2BE(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCS_HBC_MCS2BE_SHIFT)) & GTMDI_MCS_HBC_MCS2BE_MASK) 1087 1088 #define GTMDI_MCS_HBC_MCS3BE_MASK (0x8U) 1089 #define GTMDI_MCS_HBC_MCS3BE_SHIFT (3U) 1090 #define GTMDI_MCS_HBC_MCS3BE_WIDTH (1U) 1091 #define GTMDI_MCS_HBC_MCS3BE(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCS_HBC_MCS3BE_SHIFT)) & GTMDI_MCS_HBC_MCS3BE_MASK) 1092 /*! @} */ 1093 1094 /*! @name MCS_HLT - MCS Halt Control */ 1095 /*! @{ */ 1096 1097 #define GTMDI_MCS_HLT_MCS0HBP0ICLR_MASK (0x1U) 1098 #define GTMDI_MCS_HLT_MCS0HBP0ICLR_SHIFT (0U) 1099 #define GTMDI_MCS_HLT_MCS0HBP0ICLR_WIDTH (1U) 1100 #define GTMDI_MCS_HLT_MCS0HBP0ICLR(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCS_HLT_MCS0HBP0ICLR_SHIFT)) & GTMDI_MCS_HLT_MCS0HBP0ICLR_MASK) 1101 1102 #define GTMDI_MCS_HLT_MCS0HBP1ICLR_MASK (0x2U) 1103 #define GTMDI_MCS_HLT_MCS0HBP1ICLR_SHIFT (1U) 1104 #define GTMDI_MCS_HLT_MCS0HBP1ICLR_WIDTH (1U) 1105 #define GTMDI_MCS_HLT_MCS0HBP1ICLR(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCS_HLT_MCS0HBP1ICLR_SHIFT)) & GTMDI_MCS_HLT_MCS0HBP1ICLR_MASK) 1106 1107 #define GTMDI_MCS_HLT_MCS1HBP0ICLR_MASK (0x4U) 1108 #define GTMDI_MCS_HLT_MCS1HBP0ICLR_SHIFT (2U) 1109 #define GTMDI_MCS_HLT_MCS1HBP0ICLR_WIDTH (1U) 1110 #define GTMDI_MCS_HLT_MCS1HBP0ICLR(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCS_HLT_MCS1HBP0ICLR_SHIFT)) & GTMDI_MCS_HLT_MCS1HBP0ICLR_MASK) 1111 1112 #define GTMDI_MCS_HLT_MCS1HBP1ICLR_MASK (0x8U) 1113 #define GTMDI_MCS_HLT_MCS1HBP1ICLR_SHIFT (3U) 1114 #define GTMDI_MCS_HLT_MCS1HBP1ICLR_WIDTH (1U) 1115 #define GTMDI_MCS_HLT_MCS1HBP1ICLR(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCS_HLT_MCS1HBP1ICLR_SHIFT)) & GTMDI_MCS_HLT_MCS1HBP1ICLR_MASK) 1116 1117 #define GTMDI_MCS_HLT_MCS2HBP0ICLR_MASK (0x10U) 1118 #define GTMDI_MCS_HLT_MCS2HBP0ICLR_SHIFT (4U) 1119 #define GTMDI_MCS_HLT_MCS2HBP0ICLR_WIDTH (1U) 1120 #define GTMDI_MCS_HLT_MCS2HBP0ICLR(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCS_HLT_MCS2HBP0ICLR_SHIFT)) & GTMDI_MCS_HLT_MCS2HBP0ICLR_MASK) 1121 1122 #define GTMDI_MCS_HLT_MCS2HBP1ICLR_MASK (0x20U) 1123 #define GTMDI_MCS_HLT_MCS2HBP1ICLR_SHIFT (5U) 1124 #define GTMDI_MCS_HLT_MCS2HBP1ICLR_WIDTH (1U) 1125 #define GTMDI_MCS_HLT_MCS2HBP1ICLR(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCS_HLT_MCS2HBP1ICLR_SHIFT)) & GTMDI_MCS_HLT_MCS2HBP1ICLR_MASK) 1126 1127 #define GTMDI_MCS_HLT_MCS3HBP0ICLR_MASK (0x40U) 1128 #define GTMDI_MCS_HLT_MCS3HBP0ICLR_SHIFT (6U) 1129 #define GTMDI_MCS_HLT_MCS3HBP0ICLR_WIDTH (1U) 1130 #define GTMDI_MCS_HLT_MCS3HBP0ICLR(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCS_HLT_MCS3HBP0ICLR_SHIFT)) & GTMDI_MCS_HLT_MCS3HBP0ICLR_MASK) 1131 1132 #define GTMDI_MCS_HLT_MCS3HBP1ICLR_MASK (0x80U) 1133 #define GTMDI_MCS_HLT_MCS3HBP1ICLR_SHIFT (7U) 1134 #define GTMDI_MCS_HLT_MCS3HBP1ICLR_WIDTH (1U) 1135 #define GTMDI_MCS_HLT_MCS3HBP1ICLR(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCS_HLT_MCS3HBP1ICLR_SHIFT)) & GTMDI_MCS_HLT_MCS3HBP1ICLR_MASK) 1136 1137 #define GTMDI_MCS_HLT_MCSSS_MASK (0x8000U) 1138 #define GTMDI_MCS_HLT_MCSSS_SHIFT (15U) 1139 #define GTMDI_MCS_HLT_MCSSS_WIDTH (1U) 1140 #define GTMDI_MCS_HLT_MCSSS(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCS_HLT_MCSSS_SHIFT)) & GTMDI_MCS_HLT_MCSSS_MASK) 1141 1142 #define GTMDI_MCS_HLT_MCS0HBP0IS_MASK (0x10000U) 1143 #define GTMDI_MCS_HLT_MCS0HBP0IS_SHIFT (16U) 1144 #define GTMDI_MCS_HLT_MCS0HBP0IS_WIDTH (1U) 1145 #define GTMDI_MCS_HLT_MCS0HBP0IS(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCS_HLT_MCS0HBP0IS_SHIFT)) & GTMDI_MCS_HLT_MCS0HBP0IS_MASK) 1146 1147 #define GTMDI_MCS_HLT_MCS0HBP1IS_MASK (0x20000U) 1148 #define GTMDI_MCS_HLT_MCS0HBP1IS_SHIFT (17U) 1149 #define GTMDI_MCS_HLT_MCS0HBP1IS_WIDTH (1U) 1150 #define GTMDI_MCS_HLT_MCS0HBP1IS(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCS_HLT_MCS0HBP1IS_SHIFT)) & GTMDI_MCS_HLT_MCS0HBP1IS_MASK) 1151 1152 #define GTMDI_MCS_HLT_MCS1HBP0IS_MASK (0x40000U) 1153 #define GTMDI_MCS_HLT_MCS1HBP0IS_SHIFT (18U) 1154 #define GTMDI_MCS_HLT_MCS1HBP0IS_WIDTH (1U) 1155 #define GTMDI_MCS_HLT_MCS1HBP0IS(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCS_HLT_MCS1HBP0IS_SHIFT)) & GTMDI_MCS_HLT_MCS1HBP0IS_MASK) 1156 1157 #define GTMDI_MCS_HLT_MCS1HBP1IS_MASK (0x80000U) 1158 #define GTMDI_MCS_HLT_MCS1HBP1IS_SHIFT (19U) 1159 #define GTMDI_MCS_HLT_MCS1HBP1IS_WIDTH (1U) 1160 #define GTMDI_MCS_HLT_MCS1HBP1IS(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCS_HLT_MCS1HBP1IS_SHIFT)) & GTMDI_MCS_HLT_MCS1HBP1IS_MASK) 1161 1162 #define GTMDI_MCS_HLT_MCS2HBP0IS_MASK (0x100000U) 1163 #define GTMDI_MCS_HLT_MCS2HBP0IS_SHIFT (20U) 1164 #define GTMDI_MCS_HLT_MCS2HBP0IS_WIDTH (1U) 1165 #define GTMDI_MCS_HLT_MCS2HBP0IS(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCS_HLT_MCS2HBP0IS_SHIFT)) & GTMDI_MCS_HLT_MCS2HBP0IS_MASK) 1166 1167 #define GTMDI_MCS_HLT_MCS2HBP1IS_MASK (0x200000U) 1168 #define GTMDI_MCS_HLT_MCS2HBP1IS_SHIFT (21U) 1169 #define GTMDI_MCS_HLT_MCS2HBP1IS_WIDTH (1U) 1170 #define GTMDI_MCS_HLT_MCS2HBP1IS(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCS_HLT_MCS2HBP1IS_SHIFT)) & GTMDI_MCS_HLT_MCS2HBP1IS_MASK) 1171 1172 #define GTMDI_MCS_HLT_MCS3HBP0IS_MASK (0x400000U) 1173 #define GTMDI_MCS_HLT_MCS3HBP0IS_SHIFT (22U) 1174 #define GTMDI_MCS_HLT_MCS3HBP0IS_WIDTH (1U) 1175 #define GTMDI_MCS_HLT_MCS3HBP0IS(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCS_HLT_MCS3HBP0IS_SHIFT)) & GTMDI_MCS_HLT_MCS3HBP0IS_MASK) 1176 1177 #define GTMDI_MCS_HLT_MCS3HBP1IS_MASK (0x800000U) 1178 #define GTMDI_MCS_HLT_MCS3HBP1IS_SHIFT (23U) 1179 #define GTMDI_MCS_HLT_MCS3HBP1IS_WIDTH (1U) 1180 #define GTMDI_MCS_HLT_MCS3HBP1IS(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCS_HLT_MCS3HBP1IS_SHIFT)) & GTMDI_MCS_HLT_MCS3HBP1IS_MASK) 1181 1182 #define GTMDI_MCS_HLT_HALTSTAT_MASK (0x7000000U) 1183 #define GTMDI_MCS_HLT_HALTSTAT_SHIFT (24U) 1184 #define GTMDI_MCS_HLT_HALTSTAT_WIDTH (3U) 1185 #define GTMDI_MCS_HLT_HALTSTAT(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCS_HLT_HALTSTAT_SHIFT)) & GTMDI_MCS_HLT_HALTSTAT_MASK) 1186 /*! @} */ 1187 1188 /*! @name MCSA_DC - MCSA Development Control */ 1189 /*! @{ */ 1190 1191 #define GTMDI_MCSA_DC_MCS_SEL_MASK (0x300U) 1192 #define GTMDI_MCSA_DC_MCS_SEL_SHIFT (8U) 1193 #define GTMDI_MCSA_DC_MCS_SEL_WIDTH (2U) 1194 #define GTMDI_MCSA_DC_MCS_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_DC_MCS_SEL_SHIFT)) & GTMDI_MCSA_DC_MCS_SEL_MASK) 1195 1196 #define GTMDI_MCSA_DC_INDA_MASK (0x80000000U) 1197 #define GTMDI_MCSA_DC_INDA_SHIFT (31U) 1198 #define GTMDI_MCSA_DC_INDA_WIDTH (1U) 1199 #define GTMDI_MCSA_DC_INDA(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_DC_INDA_SHIFT)) & GTMDI_MCSA_DC_INDA_MASK) 1200 /*! @} */ 1201 1202 /*! @name MCSA_WPC - MCSA Watchpoint Control */ 1203 /*! @{ */ 1204 1205 #define GTMDI_MCSA_WPC_SEN_MASK (0x1U) 1206 #define GTMDI_MCSA_WPC_SEN_SHIFT (0U) 1207 #define GTMDI_MCSA_WPC_SEN_WIDTH (1U) 1208 #define GTMDI_MCSA_WPC_SEN(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_WPC_SEN_SHIFT)) & GTMDI_MCSA_WPC_SEN_MASK) 1209 1210 #define GTMDI_MCSA_WPC_TEN_MASK (0x2U) 1211 #define GTMDI_MCSA_WPC_TEN_SHIFT (1U) 1212 #define GTMDI_MCSA_WPC_TEN_WIDTH (1U) 1213 #define GTMDI_MCSA_WPC_TEN(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_WPC_TEN_SHIFT)) & GTMDI_MCSA_WPC_TEN_MASK) 1214 1215 #define GTMDI_MCSA_WPC_STSEL_MASK (0x30U) 1216 #define GTMDI_MCSA_WPC_STSEL_SHIFT (4U) 1217 #define GTMDI_MCSA_WPC_STSEL_WIDTH (2U) 1218 #define GTMDI_MCSA_WPC_STSEL(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_WPC_STSEL_SHIFT)) & GTMDI_MCSA_WPC_STSEL_MASK) 1219 1220 #define GTMDI_MCSA_WPC_HEN_MASK (0x80U) 1221 #define GTMDI_MCSA_WPC_HEN_SHIFT (7U) 1222 #define GTMDI_MCSA_WPC_HEN_WIDTH (1U) 1223 #define GTMDI_MCSA_WPC_HEN(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_WPC_HEN_SHIFT)) & GTMDI_MCSA_WPC_HEN_MASK) 1224 1225 #define GTMDI_MCSA_WPC_EOC_MASK (0x100U) 1226 #define GTMDI_MCSA_WPC_EOC_SHIFT (8U) 1227 #define GTMDI_MCSA_WPC_EOC_WIDTH (1U) 1228 #define GTMDI_MCSA_WPC_EOC(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_WPC_EOC_SHIFT)) & GTMDI_MCSA_WPC_EOC_MASK) 1229 1230 #define GTMDI_MCSA_WPC_HWO_MASK (0xC000U) 1231 #define GTMDI_MCSA_WPC_HWO_SHIFT (14U) 1232 #define GTMDI_MCSA_WPC_HWO_WIDTH (2U) 1233 #define GTMDI_MCSA_WPC_HWO(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_WPC_HWO_SHIFT)) & GTMDI_MCSA_WPC_HWO_MASK) 1234 1235 #define GTMDI_MCSA_WPC_HME_MASK (0xF0000U) 1236 #define GTMDI_MCSA_WPC_HME_SHIFT (16U) 1237 #define GTMDI_MCSA_WPC_HME_WIDTH (4U) 1238 #define GTMDI_MCSA_WPC_HME(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_WPC_HME_SHIFT)) & GTMDI_MCSA_WPC_HME_MASK) 1239 1240 #define GTMDI_MCSA_WPC_WMC_MASK (0x400000U) 1241 #define GTMDI_MCSA_WPC_WMC_SHIFT (22U) 1242 #define GTMDI_MCSA_WPC_WMC_WIDTH (1U) 1243 #define GTMDI_MCSA_WPC_WMC(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_WPC_WMC_SHIFT)) & GTMDI_MCSA_WPC_WMC_MASK) 1244 1245 #define GTMDI_MCSA_WPC_HACH_MASK (0x3000000U) 1246 #define GTMDI_MCSA_WPC_HACH_SHIFT (24U) 1247 #define GTMDI_MCSA_WPC_HACH_WIDTH (2U) 1248 #define GTMDI_MCSA_WPC_HACH(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_WPC_HACH_SHIFT)) & GTMDI_MCSA_WPC_HACH_MASK) 1249 /*! @} */ 1250 1251 /*! @name MCSA_PTC - MCSA Program Fetch Trace Control */ 1252 /*! @{ */ 1253 1254 #define GTMDI_MCSA_PTC_SEN_MASK (0x1U) 1255 #define GTMDI_MCSA_PTC_SEN_SHIFT (0U) 1256 #define GTMDI_MCSA_PTC_SEN_WIDTH (1U) 1257 #define GTMDI_MCSA_PTC_SEN(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_PTC_SEN_SHIFT)) & GTMDI_MCSA_PTC_SEN_MASK) 1258 1259 #define GTMDI_MCSA_PTC_FTC_MASK (0x40U) 1260 #define GTMDI_MCSA_PTC_FTC_SHIFT (6U) 1261 #define GTMDI_MCSA_PTC_FTC_WIDTH (1U) 1262 #define GTMDI_MCSA_PTC_FTC(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_PTC_FTC_SHIFT)) & GTMDI_MCSA_PTC_FTC_MASK) 1263 1264 #define GTMDI_MCSA_PTC_PFTE_MASK (0x300U) 1265 #define GTMDI_MCSA_PTC_PFTE_SHIFT (8U) 1266 #define GTMDI_MCSA_PTC_PFTE_WIDTH (2U) 1267 #define GTMDI_MCSA_PTC_PFTE(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_PTC_PFTE_SHIFT)) & GTMDI_MCSA_PTC_PFTE_MASK) 1268 1269 #define GTMDI_MCSA_PTC_PFTS_MASK (0x3000U) 1270 #define GTMDI_MCSA_PTC_PFTS_SHIFT (12U) 1271 #define GTMDI_MCSA_PTC_PFTS_WIDTH (2U) 1272 #define GTMDI_MCSA_PTC_PFTS(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_PTC_PFTS_SHIFT)) & GTMDI_MCSA_PTC_PFTS_MASK) 1273 /*! @} */ 1274 1275 /*! @name MCSA_DTC - MCSA Data Trace Control */ 1276 /*! @{ */ 1277 1278 #define GTMDI_MCSA_DTC_SEN_MASK (0x1U) 1279 #define GTMDI_MCSA_DTC_SEN_SHIFT (0U) 1280 #define GTMDI_MCSA_DTC_SEN_WIDTH (1U) 1281 #define GTMDI_MCSA_DTC_SEN(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_DTC_SEN_SHIFT)) & GTMDI_MCSA_DTC_SEN_MASK) 1282 1283 #define GTMDI_MCSA_DTC_DTE_MASK (0x6U) 1284 #define GTMDI_MCSA_DTC_DTE_SHIFT (1U) 1285 #define GTMDI_MCSA_DTC_DTE_WIDTH (2U) 1286 #define GTMDI_MCSA_DTC_DTE(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_DTC_DTE_SHIFT)) & GTMDI_MCSA_DTC_DTE_MASK) 1287 1288 #define GTMDI_MCSA_DTC_DTS_MASK (0x30U) 1289 #define GTMDI_MCSA_DTC_DTS_SHIFT (4U) 1290 #define GTMDI_MCSA_DTC_DTS_WIDTH (2U) 1291 #define GTMDI_MCSA_DTC_DTS(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_DTC_DTS_SHIFT)) & GTMDI_MCSA_DTC_DTS_MASK) 1292 1293 #define GTMDI_MCSA_DTC_DTC_MASK (0x40U) 1294 #define GTMDI_MCSA_DTC_DTC_SHIFT (6U) 1295 #define GTMDI_MCSA_DTC_DTC_WIDTH (1U) 1296 #define GTMDI_MCSA_DTC_DTC(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_DTC_DTC_SHIFT)) & GTMDI_MCSA_DTC_DTC_MASK) 1297 1298 #define GTMDI_MCSA_DTC_RWT1_MASK (0x300U) 1299 #define GTMDI_MCSA_DTC_RWT1_SHIFT (8U) 1300 #define GTMDI_MCSA_DTC_RWT1_WIDTH (2U) 1301 #define GTMDI_MCSA_DTC_RWT1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_DTC_RWT1_SHIFT)) & GTMDI_MCSA_DTC_RWT1_MASK) 1302 1303 #define GTMDI_MCSA_DTC_RWT0_MASK (0x3000U) 1304 #define GTMDI_MCSA_DTC_RWT0_SHIFT (12U) 1305 #define GTMDI_MCSA_DTC_RWT0_WIDTH (2U) 1306 #define GTMDI_MCSA_DTC_RWT0(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_DTC_RWT0_SHIFT)) & GTMDI_MCSA_DTC_RWT0_MASK) 1307 1308 #define GTMDI_MCSA_DTC_RC1_MASK (0x10000U) 1309 #define GTMDI_MCSA_DTC_RC1_SHIFT (16U) 1310 #define GTMDI_MCSA_DTC_RC1_WIDTH (1U) 1311 #define GTMDI_MCSA_DTC_RC1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_DTC_RC1_SHIFT)) & GTMDI_MCSA_DTC_RC1_MASK) 1312 1313 #define GTMDI_MCSA_DTC_RC0_MASK (0x20000U) 1314 #define GTMDI_MCSA_DTC_RC0_SHIFT (17U) 1315 #define GTMDI_MCSA_DTC_RC0_WIDTH (1U) 1316 #define GTMDI_MCSA_DTC_RC0(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_DTC_RC0_SHIFT)) & GTMDI_MCSA_DTC_RC0_MASK) 1317 /*! @} */ 1318 1319 /*! @name MCSA_WPA1 - MCSA Watchpoint Address 1 */ 1320 /*! @{ */ 1321 1322 #define GTMDI_MCSA_WPA1_HWA_MASK (0x3FFFU) 1323 #define GTMDI_MCSA_WPA1_HWA_SHIFT (0U) 1324 #define GTMDI_MCSA_WPA1_HWA_WIDTH (14U) 1325 #define GTMDI_MCSA_WPA1_HWA(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_WPA1_HWA_SHIFT)) & GTMDI_MCSA_WPA1_HWA_MASK) 1326 1327 #define GTMDI_MCSA_WPA1_HWAM_MASK (0x3FFF0000U) 1328 #define GTMDI_MCSA_WPA1_HWAM_SHIFT (16U) 1329 #define GTMDI_MCSA_WPA1_HWAM_WIDTH (14U) 1330 #define GTMDI_MCSA_WPA1_HWAM(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_WPA1_HWAM_SHIFT)) & GTMDI_MCSA_WPA1_HWAM_MASK) 1331 /*! @} */ 1332 1333 /*! @name MCSA_WPA2 - MCSA Watchpoint Address 2 */ 1334 /*! @{ */ 1335 1336 #define GTMDI_MCSA_WPA2_HWA_MASK (0x3FFFU) 1337 #define GTMDI_MCSA_WPA2_HWA_SHIFT (0U) 1338 #define GTMDI_MCSA_WPA2_HWA_WIDTH (14U) 1339 #define GTMDI_MCSA_WPA2_HWA(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_WPA2_HWA_SHIFT)) & GTMDI_MCSA_WPA2_HWA_MASK) 1340 1341 #define GTMDI_MCSA_WPA2_HWAM_MASK (0x3FFF0000U) 1342 #define GTMDI_MCSA_WPA2_HWAM_SHIFT (16U) 1343 #define GTMDI_MCSA_WPA2_HWAM_WIDTH (14U) 1344 #define GTMDI_MCSA_WPA2_HWAM(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_WPA2_HWAM_SHIFT)) & GTMDI_MCSA_WPA2_HWAM_MASK) 1345 /*! @} */ 1346 1347 /*! @name MCSA_WPD1 - MCSA Watchpoint Data 1 */ 1348 /*! @{ */ 1349 1350 #define GTMDI_MCSA_WPD1_HWD_MASK (0xFFFFFFFFU) 1351 #define GTMDI_MCSA_WPD1_HWD_SHIFT (0U) 1352 #define GTMDI_MCSA_WPD1_HWD_WIDTH (32U) 1353 #define GTMDI_MCSA_WPD1_HWD(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_WPD1_HWD_SHIFT)) & GTMDI_MCSA_WPD1_HWD_MASK) 1354 /*! @} */ 1355 1356 /*! @name MCSA_WPD2 - MCSA Watchpoint Data 2 */ 1357 /*! @{ */ 1358 1359 #define GTMDI_MCSA_WPD2_HWD_MASK (0xFFFFFFFFU) 1360 #define GTMDI_MCSA_WPD2_HWD_SHIFT (0U) 1361 #define GTMDI_MCSA_WPD2_HWD_WIDTH (32U) 1362 #define GTMDI_MCSA_WPD2_HWD(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_WPD2_HWD_SHIFT)) & GTMDI_MCSA_WPD2_HWD_MASK) 1363 /*! @} */ 1364 1365 /*! @name MCSA_CE - MCSA Channel Enable */ 1366 /*! @{ */ 1367 1368 #define GTMDI_MCSA_CE_WPCE_MASK (0xFFU) 1369 #define GTMDI_MCSA_CE_WPCE_SHIFT (0U) 1370 #define GTMDI_MCSA_CE_WPCE_WIDTH (8U) 1371 #define GTMDI_MCSA_CE_WPCE(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_CE_WPCE_SHIFT)) & GTMDI_MCSA_CE_WPCE_MASK) 1372 1373 #define GTMDI_MCSA_CE_CDTE_MASK (0xFF0000U) 1374 #define GTMDI_MCSA_CE_CDTE_SHIFT (16U) 1375 #define GTMDI_MCSA_CE_CDTE_WIDTH (8U) 1376 #define GTMDI_MCSA_CE_CDTE(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_CE_CDTE_SHIFT)) & GTMDI_MCSA_CE_CDTE_MASK) 1377 1378 #define GTMDI_MCSA_CE_CFTE_MASK (0xFF000000U) 1379 #define GTMDI_MCSA_CE_CFTE_SHIFT (24U) 1380 #define GTMDI_MCSA_CE_CFTE_WIDTH (8U) 1381 #define GTMDI_MCSA_CE_CFTE(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_CE_CFTE_SHIFT)) & GTMDI_MCSA_CE_CFTE_MASK) 1382 /*! @} */ 1383 1384 /*! @name MCSA_DTAR1 - MCSA Data Trace Address Range 1 */ 1385 /*! @{ */ 1386 1387 #define GTMDI_MCSA_DTAR1_DTEA_MASK (0x7FFCU) 1388 #define GTMDI_MCSA_DTAR1_DTEA_SHIFT (2U) 1389 #define GTMDI_MCSA_DTAR1_DTEA_WIDTH (13U) 1390 #define GTMDI_MCSA_DTAR1_DTEA(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_DTAR1_DTEA_SHIFT)) & GTMDI_MCSA_DTAR1_DTEA_MASK) 1391 1392 #define GTMDI_MCSA_DTAR1_DTSA_MASK (0x7FFC0000U) 1393 #define GTMDI_MCSA_DTAR1_DTSA_SHIFT (18U) 1394 #define GTMDI_MCSA_DTAR1_DTSA_WIDTH (13U) 1395 #define GTMDI_MCSA_DTAR1_DTSA(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_DTAR1_DTSA_SHIFT)) & GTMDI_MCSA_DTAR1_DTSA_MASK) 1396 /*! @} */ 1397 1398 /*! @name MCSA_DTAR2 - MCSA Data Trace Address Range 2 */ 1399 /*! @{ */ 1400 1401 #define GTMDI_MCSA_DTAR2_DTEA_MASK (0x7FFCU) 1402 #define GTMDI_MCSA_DTAR2_DTEA_SHIFT (2U) 1403 #define GTMDI_MCSA_DTAR2_DTEA_WIDTH (13U) 1404 #define GTMDI_MCSA_DTAR2_DTEA(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_DTAR2_DTEA_SHIFT)) & GTMDI_MCSA_DTAR2_DTEA_MASK) 1405 1406 #define GTMDI_MCSA_DTAR2_DTSA_MASK (0x7FFC0000U) 1407 #define GTMDI_MCSA_DTAR2_DTSA_SHIFT (18U) 1408 #define GTMDI_MCSA_DTAR2_DTSA_WIDTH (13U) 1409 #define GTMDI_MCSA_DTAR2_DTSA(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSA_DTAR2_DTSA_SHIFT)) & GTMDI_MCSA_DTAR2_DTSA_MASK) 1410 /*! @} */ 1411 1412 /*! @name MCSB_DC - MCSB Development Control */ 1413 /*! @{ */ 1414 1415 #define GTMDI_MCSB_DC_MCS_SEL_MASK (0x300U) 1416 #define GTMDI_MCSB_DC_MCS_SEL_SHIFT (8U) 1417 #define GTMDI_MCSB_DC_MCS_SEL_WIDTH (2U) 1418 #define GTMDI_MCSB_DC_MCS_SEL(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_DC_MCS_SEL_SHIFT)) & GTMDI_MCSB_DC_MCS_SEL_MASK) 1419 1420 #define GTMDI_MCSB_DC_INDA_MASK (0x80000000U) 1421 #define GTMDI_MCSB_DC_INDA_SHIFT (31U) 1422 #define GTMDI_MCSB_DC_INDA_WIDTH (1U) 1423 #define GTMDI_MCSB_DC_INDA(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_DC_INDA_SHIFT)) & GTMDI_MCSB_DC_INDA_MASK) 1424 /*! @} */ 1425 1426 /*! @name MCSB_WPC - MCSB Watchpoint Control */ 1427 /*! @{ */ 1428 1429 #define GTMDI_MCSB_WPC_SEN_MASK (0x1U) 1430 #define GTMDI_MCSB_WPC_SEN_SHIFT (0U) 1431 #define GTMDI_MCSB_WPC_SEN_WIDTH (1U) 1432 #define GTMDI_MCSB_WPC_SEN(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_WPC_SEN_SHIFT)) & GTMDI_MCSB_WPC_SEN_MASK) 1433 1434 #define GTMDI_MCSB_WPC_TEN_MASK (0x2U) 1435 #define GTMDI_MCSB_WPC_TEN_SHIFT (1U) 1436 #define GTMDI_MCSB_WPC_TEN_WIDTH (1U) 1437 #define GTMDI_MCSB_WPC_TEN(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_WPC_TEN_SHIFT)) & GTMDI_MCSB_WPC_TEN_MASK) 1438 1439 #define GTMDI_MCSB_WPC_STSEL_MASK (0x30U) 1440 #define GTMDI_MCSB_WPC_STSEL_SHIFT (4U) 1441 #define GTMDI_MCSB_WPC_STSEL_WIDTH (2U) 1442 #define GTMDI_MCSB_WPC_STSEL(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_WPC_STSEL_SHIFT)) & GTMDI_MCSB_WPC_STSEL_MASK) 1443 1444 #define GTMDI_MCSB_WPC_HEN_MASK (0x80U) 1445 #define GTMDI_MCSB_WPC_HEN_SHIFT (7U) 1446 #define GTMDI_MCSB_WPC_HEN_WIDTH (1U) 1447 #define GTMDI_MCSB_WPC_HEN(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_WPC_HEN_SHIFT)) & GTMDI_MCSB_WPC_HEN_MASK) 1448 1449 #define GTMDI_MCSB_WPC_EOC_MASK (0x100U) 1450 #define GTMDI_MCSB_WPC_EOC_SHIFT (8U) 1451 #define GTMDI_MCSB_WPC_EOC_WIDTH (1U) 1452 #define GTMDI_MCSB_WPC_EOC(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_WPC_EOC_SHIFT)) & GTMDI_MCSB_WPC_EOC_MASK) 1453 1454 #define GTMDI_MCSB_WPC_HWO_MASK (0xC000U) 1455 #define GTMDI_MCSB_WPC_HWO_SHIFT (14U) 1456 #define GTMDI_MCSB_WPC_HWO_WIDTH (2U) 1457 #define GTMDI_MCSB_WPC_HWO(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_WPC_HWO_SHIFT)) & GTMDI_MCSB_WPC_HWO_MASK) 1458 1459 #define GTMDI_MCSB_WPC_HME_MASK (0xF0000U) 1460 #define GTMDI_MCSB_WPC_HME_SHIFT (16U) 1461 #define GTMDI_MCSB_WPC_HME_WIDTH (4U) 1462 #define GTMDI_MCSB_WPC_HME(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_WPC_HME_SHIFT)) & GTMDI_MCSB_WPC_HME_MASK) 1463 1464 #define GTMDI_MCSB_WPC_WMC_MASK (0x400000U) 1465 #define GTMDI_MCSB_WPC_WMC_SHIFT (22U) 1466 #define GTMDI_MCSB_WPC_WMC_WIDTH (1U) 1467 #define GTMDI_MCSB_WPC_WMC(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_WPC_WMC_SHIFT)) & GTMDI_MCSB_WPC_WMC_MASK) 1468 1469 #define GTMDI_MCSB_WPC_HACH_MASK (0x3000000U) 1470 #define GTMDI_MCSB_WPC_HACH_SHIFT (24U) 1471 #define GTMDI_MCSB_WPC_HACH_WIDTH (2U) 1472 #define GTMDI_MCSB_WPC_HACH(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_WPC_HACH_SHIFT)) & GTMDI_MCSB_WPC_HACH_MASK) 1473 /*! @} */ 1474 1475 /*! @name MCSB_PTC - MCSB Program Fetch Trace Control */ 1476 /*! @{ */ 1477 1478 #define GTMDI_MCSB_PTC_SEN_MASK (0x1U) 1479 #define GTMDI_MCSB_PTC_SEN_SHIFT (0U) 1480 #define GTMDI_MCSB_PTC_SEN_WIDTH (1U) 1481 #define GTMDI_MCSB_PTC_SEN(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_PTC_SEN_SHIFT)) & GTMDI_MCSB_PTC_SEN_MASK) 1482 1483 #define GTMDI_MCSB_PTC_FTC_MASK (0x40U) 1484 #define GTMDI_MCSB_PTC_FTC_SHIFT (6U) 1485 #define GTMDI_MCSB_PTC_FTC_WIDTH (1U) 1486 #define GTMDI_MCSB_PTC_FTC(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_PTC_FTC_SHIFT)) & GTMDI_MCSB_PTC_FTC_MASK) 1487 1488 #define GTMDI_MCSB_PTC_PFTE_MASK (0x300U) 1489 #define GTMDI_MCSB_PTC_PFTE_SHIFT (8U) 1490 #define GTMDI_MCSB_PTC_PFTE_WIDTH (2U) 1491 #define GTMDI_MCSB_PTC_PFTE(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_PTC_PFTE_SHIFT)) & GTMDI_MCSB_PTC_PFTE_MASK) 1492 1493 #define GTMDI_MCSB_PTC_PFTS_MASK (0x3000U) 1494 #define GTMDI_MCSB_PTC_PFTS_SHIFT (12U) 1495 #define GTMDI_MCSB_PTC_PFTS_WIDTH (2U) 1496 #define GTMDI_MCSB_PTC_PFTS(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_PTC_PFTS_SHIFT)) & GTMDI_MCSB_PTC_PFTS_MASK) 1497 /*! @} */ 1498 1499 /*! @name MCSB_DTC - MCSB Data Trace Control */ 1500 /*! @{ */ 1501 1502 #define GTMDI_MCSB_DTC_SEN_MASK (0x1U) 1503 #define GTMDI_MCSB_DTC_SEN_SHIFT (0U) 1504 #define GTMDI_MCSB_DTC_SEN_WIDTH (1U) 1505 #define GTMDI_MCSB_DTC_SEN(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_DTC_SEN_SHIFT)) & GTMDI_MCSB_DTC_SEN_MASK) 1506 1507 #define GTMDI_MCSB_DTC_DTE_MASK (0x6U) 1508 #define GTMDI_MCSB_DTC_DTE_SHIFT (1U) 1509 #define GTMDI_MCSB_DTC_DTE_WIDTH (2U) 1510 #define GTMDI_MCSB_DTC_DTE(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_DTC_DTE_SHIFT)) & GTMDI_MCSB_DTC_DTE_MASK) 1511 1512 #define GTMDI_MCSB_DTC_DTS_MASK (0x30U) 1513 #define GTMDI_MCSB_DTC_DTS_SHIFT (4U) 1514 #define GTMDI_MCSB_DTC_DTS_WIDTH (2U) 1515 #define GTMDI_MCSB_DTC_DTS(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_DTC_DTS_SHIFT)) & GTMDI_MCSB_DTC_DTS_MASK) 1516 1517 #define GTMDI_MCSB_DTC_DTC_MASK (0x40U) 1518 #define GTMDI_MCSB_DTC_DTC_SHIFT (6U) 1519 #define GTMDI_MCSB_DTC_DTC_WIDTH (1U) 1520 #define GTMDI_MCSB_DTC_DTC(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_DTC_DTC_SHIFT)) & GTMDI_MCSB_DTC_DTC_MASK) 1521 1522 #define GTMDI_MCSB_DTC_RWT1_MASK (0x300U) 1523 #define GTMDI_MCSB_DTC_RWT1_SHIFT (8U) 1524 #define GTMDI_MCSB_DTC_RWT1_WIDTH (2U) 1525 #define GTMDI_MCSB_DTC_RWT1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_DTC_RWT1_SHIFT)) & GTMDI_MCSB_DTC_RWT1_MASK) 1526 1527 #define GTMDI_MCSB_DTC_RWT0_MASK (0x3000U) 1528 #define GTMDI_MCSB_DTC_RWT0_SHIFT (12U) 1529 #define GTMDI_MCSB_DTC_RWT0_WIDTH (2U) 1530 #define GTMDI_MCSB_DTC_RWT0(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_DTC_RWT0_SHIFT)) & GTMDI_MCSB_DTC_RWT0_MASK) 1531 1532 #define GTMDI_MCSB_DTC_RC1_MASK (0x10000U) 1533 #define GTMDI_MCSB_DTC_RC1_SHIFT (16U) 1534 #define GTMDI_MCSB_DTC_RC1_WIDTH (1U) 1535 #define GTMDI_MCSB_DTC_RC1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_DTC_RC1_SHIFT)) & GTMDI_MCSB_DTC_RC1_MASK) 1536 1537 #define GTMDI_MCSB_DTC_RC0_MASK (0x20000U) 1538 #define GTMDI_MCSB_DTC_RC0_SHIFT (17U) 1539 #define GTMDI_MCSB_DTC_RC0_WIDTH (1U) 1540 #define GTMDI_MCSB_DTC_RC0(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_DTC_RC0_SHIFT)) & GTMDI_MCSB_DTC_RC0_MASK) 1541 /*! @} */ 1542 1543 /*! @name MCSB_WPA1 - MCSB Watchpoint Address 1 */ 1544 /*! @{ */ 1545 1546 #define GTMDI_MCSB_WPA1_HWA_MASK (0x3FFFU) 1547 #define GTMDI_MCSB_WPA1_HWA_SHIFT (0U) 1548 #define GTMDI_MCSB_WPA1_HWA_WIDTH (14U) 1549 #define GTMDI_MCSB_WPA1_HWA(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_WPA1_HWA_SHIFT)) & GTMDI_MCSB_WPA1_HWA_MASK) 1550 1551 #define GTMDI_MCSB_WPA1_HWAM_MASK (0x3FFF0000U) 1552 #define GTMDI_MCSB_WPA1_HWAM_SHIFT (16U) 1553 #define GTMDI_MCSB_WPA1_HWAM_WIDTH (14U) 1554 #define GTMDI_MCSB_WPA1_HWAM(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_WPA1_HWAM_SHIFT)) & GTMDI_MCSB_WPA1_HWAM_MASK) 1555 /*! @} */ 1556 1557 /*! @name MCSB_WPA2 - MCSB Watchpoint Address 2 */ 1558 /*! @{ */ 1559 1560 #define GTMDI_MCSB_WPA2_HWA_MASK (0x3FFFU) 1561 #define GTMDI_MCSB_WPA2_HWA_SHIFT (0U) 1562 #define GTMDI_MCSB_WPA2_HWA_WIDTH (14U) 1563 #define GTMDI_MCSB_WPA2_HWA(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_WPA2_HWA_SHIFT)) & GTMDI_MCSB_WPA2_HWA_MASK) 1564 1565 #define GTMDI_MCSB_WPA2_HWAM_MASK (0x3FFF0000U) 1566 #define GTMDI_MCSB_WPA2_HWAM_SHIFT (16U) 1567 #define GTMDI_MCSB_WPA2_HWAM_WIDTH (14U) 1568 #define GTMDI_MCSB_WPA2_HWAM(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_WPA2_HWAM_SHIFT)) & GTMDI_MCSB_WPA2_HWAM_MASK) 1569 /*! @} */ 1570 1571 /*! @name MCSB_WPD1 - MCSB Watchpoint Data 1 */ 1572 /*! @{ */ 1573 1574 #define GTMDI_MCSB_WPD1_HWD_MASK (0xFFFFFFFFU) 1575 #define GTMDI_MCSB_WPD1_HWD_SHIFT (0U) 1576 #define GTMDI_MCSB_WPD1_HWD_WIDTH (32U) 1577 #define GTMDI_MCSB_WPD1_HWD(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_WPD1_HWD_SHIFT)) & GTMDI_MCSB_WPD1_HWD_MASK) 1578 /*! @} */ 1579 1580 /*! @name MCSB_WPD2 - MCSB Watchpoint Data 2 */ 1581 /*! @{ */ 1582 1583 #define GTMDI_MCSB_WPD2_HWD_MASK (0xFFFFFFFFU) 1584 #define GTMDI_MCSB_WPD2_HWD_SHIFT (0U) 1585 #define GTMDI_MCSB_WPD2_HWD_WIDTH (32U) 1586 #define GTMDI_MCSB_WPD2_HWD(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_WPD2_HWD_SHIFT)) & GTMDI_MCSB_WPD2_HWD_MASK) 1587 /*! @} */ 1588 1589 /*! @name MCSB_CE - MCSB Channel Enable */ 1590 /*! @{ */ 1591 1592 #define GTMDI_MCSB_CE_WPCE_MASK (0xFFU) 1593 #define GTMDI_MCSB_CE_WPCE_SHIFT (0U) 1594 #define GTMDI_MCSB_CE_WPCE_WIDTH (8U) 1595 #define GTMDI_MCSB_CE_WPCE(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_CE_WPCE_SHIFT)) & GTMDI_MCSB_CE_WPCE_MASK) 1596 1597 #define GTMDI_MCSB_CE_CDTE_MASK (0xFF0000U) 1598 #define GTMDI_MCSB_CE_CDTE_SHIFT (16U) 1599 #define GTMDI_MCSB_CE_CDTE_WIDTH (8U) 1600 #define GTMDI_MCSB_CE_CDTE(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_CE_CDTE_SHIFT)) & GTMDI_MCSB_CE_CDTE_MASK) 1601 1602 #define GTMDI_MCSB_CE_CFTE_MASK (0xFF000000U) 1603 #define GTMDI_MCSB_CE_CFTE_SHIFT (24U) 1604 #define GTMDI_MCSB_CE_CFTE_WIDTH (8U) 1605 #define GTMDI_MCSB_CE_CFTE(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_CE_CFTE_SHIFT)) & GTMDI_MCSB_CE_CFTE_MASK) 1606 /*! @} */ 1607 1608 /*! @name MCSB_DTAR1 - MCSB Data Trace Address Range 1 */ 1609 /*! @{ */ 1610 1611 #define GTMDI_MCSB_DTAR1_DTEA_MASK (0x7FFCU) 1612 #define GTMDI_MCSB_DTAR1_DTEA_SHIFT (2U) 1613 #define GTMDI_MCSB_DTAR1_DTEA_WIDTH (13U) 1614 #define GTMDI_MCSB_DTAR1_DTEA(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_DTAR1_DTEA_SHIFT)) & GTMDI_MCSB_DTAR1_DTEA_MASK) 1615 1616 #define GTMDI_MCSB_DTAR1_DTSA_MASK (0x7FFC0000U) 1617 #define GTMDI_MCSB_DTAR1_DTSA_SHIFT (18U) 1618 #define GTMDI_MCSB_DTAR1_DTSA_WIDTH (13U) 1619 #define GTMDI_MCSB_DTAR1_DTSA(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_DTAR1_DTSA_SHIFT)) & GTMDI_MCSB_DTAR1_DTSA_MASK) 1620 /*! @} */ 1621 1622 /*! @name MCSB_DTAR2 - MCSB Data Trace Address Range 2 */ 1623 /*! @{ */ 1624 1625 #define GTMDI_MCSB_DTAR2_DTEA_MASK (0x7FFCU) 1626 #define GTMDI_MCSB_DTAR2_DTEA_SHIFT (2U) 1627 #define GTMDI_MCSB_DTAR2_DTEA_WIDTH (13U) 1628 #define GTMDI_MCSB_DTAR2_DTEA(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_DTAR2_DTEA_SHIFT)) & GTMDI_MCSB_DTAR2_DTEA_MASK) 1629 1630 #define GTMDI_MCSB_DTAR2_DTSA_MASK (0x7FFC0000U) 1631 #define GTMDI_MCSB_DTAR2_DTSA_SHIFT (18U) 1632 #define GTMDI_MCSB_DTAR2_DTSA_WIDTH (13U) 1633 #define GTMDI_MCSB_DTAR2_DTSA(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_MCSB_DTAR2_DTSA_SHIFT)) & GTMDI_MCSB_DTAR2_DTSA_MASK) 1634 /*! @} */ 1635 1636 /*! @name TBU0_WPC1 - TBU0 Watchpoint Control 1 */ 1637 /*! @{ */ 1638 1639 #define GTMDI_TBU0_WPC1_WMC2_MASK (0x40U) 1640 #define GTMDI_TBU0_WPC1_WMC2_SHIFT (6U) 1641 #define GTMDI_TBU0_WPC1_WMC2_WIDTH (1U) 1642 #define GTMDI_TBU0_WPC1_WMC2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU0_WPC1_WMC2_SHIFT)) & GTMDI_TBU0_WPC1_WMC2_MASK) 1643 1644 #define GTMDI_TBU0_WPC1_HEN2_MASK (0x80U) 1645 #define GTMDI_TBU0_WPC1_HEN2_SHIFT (7U) 1646 #define GTMDI_TBU0_WPC1_HEN2_WIDTH (1U) 1647 #define GTMDI_TBU0_WPC1_HEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU0_WPC1_HEN2_SHIFT)) & GTMDI_TBU0_WPC1_HEN2_MASK) 1648 1649 #define GTMDI_TBU0_WPC1_TSS2_MASK (0x7000U) 1650 #define GTMDI_TBU0_WPC1_TSS2_SHIFT (12U) 1651 #define GTMDI_TBU0_WPC1_TSS2_WIDTH (3U) 1652 #define GTMDI_TBU0_WPC1_TSS2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU0_WPC1_TSS2_SHIFT)) & GTMDI_TBU0_WPC1_TSS2_MASK) 1653 1654 #define GTMDI_TBU0_WPC1_WMC1_MASK (0x400000U) 1655 #define GTMDI_TBU0_WPC1_WMC1_SHIFT (22U) 1656 #define GTMDI_TBU0_WPC1_WMC1_WIDTH (1U) 1657 #define GTMDI_TBU0_WPC1_WMC1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU0_WPC1_WMC1_SHIFT)) & GTMDI_TBU0_WPC1_WMC1_MASK) 1658 1659 #define GTMDI_TBU0_WPC1_HEN1_MASK (0x800000U) 1660 #define GTMDI_TBU0_WPC1_HEN1_SHIFT (23U) 1661 #define GTMDI_TBU0_WPC1_HEN1_WIDTH (1U) 1662 #define GTMDI_TBU0_WPC1_HEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU0_WPC1_HEN1_SHIFT)) & GTMDI_TBU0_WPC1_HEN1_MASK) 1663 1664 #define GTMDI_TBU0_WPC1_TSS1_MASK (0x70000000U) 1665 #define GTMDI_TBU0_WPC1_TSS1_SHIFT (28U) 1666 #define GTMDI_TBU0_WPC1_TSS1_WIDTH (3U) 1667 #define GTMDI_TBU0_WPC1_TSS1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU0_WPC1_TSS1_SHIFT)) & GTMDI_TBU0_WPC1_TSS1_MASK) 1668 /*! @} */ 1669 1670 /*! @name TBU0_WPC2 - TBUn Watchpoint Control 2 */ 1671 /*! @{ */ 1672 1673 #define GTMDI_TBU0_WPC2_SEN2_MASK (0x1U) 1674 #define GTMDI_TBU0_WPC2_SEN2_SHIFT (0U) 1675 #define GTMDI_TBU0_WPC2_SEN2_WIDTH (1U) 1676 #define GTMDI_TBU0_WPC2_SEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU0_WPC2_SEN2_SHIFT)) & GTMDI_TBU0_WPC2_SEN2_MASK) 1677 1678 #define GTMDI_TBU0_WPC2_TEN2_MASK (0x2U) 1679 #define GTMDI_TBU0_WPC2_TEN2_SHIFT (1U) 1680 #define GTMDI_TBU0_WPC2_TEN2_WIDTH (1U) 1681 #define GTMDI_TBU0_WPC2_TEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU0_WPC2_TEN2_SHIFT)) & GTMDI_TBU0_WPC2_TEN2_MASK) 1682 1683 #define GTMDI_TBU0_WPC2_STSEL2_MASK (0x30U) 1684 #define GTMDI_TBU0_WPC2_STSEL2_SHIFT (4U) 1685 #define GTMDI_TBU0_WPC2_STSEL2_WIDTH (2U) 1686 #define GTMDI_TBU0_WPC2_STSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU0_WPC2_STSEL2_SHIFT)) & GTMDI_TBU0_WPC2_STSEL2_MASK) 1687 1688 #define GTMDI_TBU0_WPC2_WTSEL2_MASK (0x7000U) 1689 #define GTMDI_TBU0_WPC2_WTSEL2_SHIFT (12U) 1690 #define GTMDI_TBU0_WPC2_WTSEL2_WIDTH (3U) 1691 #define GTMDI_TBU0_WPC2_WTSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU0_WPC2_WTSEL2_SHIFT)) & GTMDI_TBU0_WPC2_WTSEL2_MASK) 1692 1693 #define GTMDI_TBU0_WPC2_SEN1_MASK (0x10000U) 1694 #define GTMDI_TBU0_WPC2_SEN1_SHIFT (16U) 1695 #define GTMDI_TBU0_WPC2_SEN1_WIDTH (1U) 1696 #define GTMDI_TBU0_WPC2_SEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU0_WPC2_SEN1_SHIFT)) & GTMDI_TBU0_WPC2_SEN1_MASK) 1697 1698 #define GTMDI_TBU0_WPC2_TEN1_MASK (0x20000U) 1699 #define GTMDI_TBU0_WPC2_TEN1_SHIFT (17U) 1700 #define GTMDI_TBU0_WPC2_TEN1_WIDTH (1U) 1701 #define GTMDI_TBU0_WPC2_TEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU0_WPC2_TEN1_SHIFT)) & GTMDI_TBU0_WPC2_TEN1_MASK) 1702 1703 #define GTMDI_TBU0_WPC2_STSEL1_MASK (0x300000U) 1704 #define GTMDI_TBU0_WPC2_STSEL1_SHIFT (20U) 1705 #define GTMDI_TBU0_WPC2_STSEL1_WIDTH (2U) 1706 #define GTMDI_TBU0_WPC2_STSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU0_WPC2_STSEL1_SHIFT)) & GTMDI_TBU0_WPC2_STSEL1_MASK) 1707 1708 #define GTMDI_TBU0_WPC2_WTSEL1_MASK (0x70000000U) 1709 #define GTMDI_TBU0_WPC2_WTSEL1_SHIFT (28U) 1710 #define GTMDI_TBU0_WPC2_WTSEL1_WIDTH (3U) 1711 #define GTMDI_TBU0_WPC2_WTSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU0_WPC2_WTSEL1_SHIFT)) & GTMDI_TBU0_WPC2_WTSEL1_MASK) 1712 /*! @} */ 1713 1714 /*! @name TBU0_D - TBU0 Watchpoint DATA */ 1715 /*! @{ */ 1716 1717 #define GTMDI_TBU0_D_TBU0_DATA_MASK (0x7FFFFFFU) 1718 #define GTMDI_TBU0_D_TBU0_DATA_SHIFT (0U) 1719 #define GTMDI_TBU0_D_TBU0_DATA_WIDTH (27U) 1720 #define GTMDI_TBU0_D_TBU0_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU0_D_TBU0_DATA_SHIFT)) & GTMDI_TBU0_D_TBU0_DATA_MASK) 1721 /*! @} */ 1722 1723 /*! @name TBU1_WPC1 - TBUn Watchpoint Control 1 */ 1724 /*! @{ */ 1725 1726 #define GTMDI_TBU1_WPC1_WMC2_MASK (0x40U) 1727 #define GTMDI_TBU1_WPC1_WMC2_SHIFT (6U) 1728 #define GTMDI_TBU1_WPC1_WMC2_WIDTH (1U) 1729 #define GTMDI_TBU1_WPC1_WMC2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU1_WPC1_WMC2_SHIFT)) & GTMDI_TBU1_WPC1_WMC2_MASK) 1730 1731 #define GTMDI_TBU1_WPC1_HEN2_MASK (0x80U) 1732 #define GTMDI_TBU1_WPC1_HEN2_SHIFT (7U) 1733 #define GTMDI_TBU1_WPC1_HEN2_WIDTH (1U) 1734 #define GTMDI_TBU1_WPC1_HEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU1_WPC1_HEN2_SHIFT)) & GTMDI_TBU1_WPC1_HEN2_MASK) 1735 1736 #define GTMDI_TBU1_WPC1_TSS2_MASK (0x3000U) 1737 #define GTMDI_TBU1_WPC1_TSS2_SHIFT (12U) 1738 #define GTMDI_TBU1_WPC1_TSS2_WIDTH (2U) 1739 #define GTMDI_TBU1_WPC1_TSS2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU1_WPC1_TSS2_SHIFT)) & GTMDI_TBU1_WPC1_TSS2_MASK) 1740 1741 #define GTMDI_TBU1_WPC1_WMC1_MASK (0x400000U) 1742 #define GTMDI_TBU1_WPC1_WMC1_SHIFT (22U) 1743 #define GTMDI_TBU1_WPC1_WMC1_WIDTH (1U) 1744 #define GTMDI_TBU1_WPC1_WMC1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU1_WPC1_WMC1_SHIFT)) & GTMDI_TBU1_WPC1_WMC1_MASK) 1745 1746 #define GTMDI_TBU1_WPC1_HEN1_MASK (0x800000U) 1747 #define GTMDI_TBU1_WPC1_HEN1_SHIFT (23U) 1748 #define GTMDI_TBU1_WPC1_HEN1_WIDTH (1U) 1749 #define GTMDI_TBU1_WPC1_HEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU1_WPC1_HEN1_SHIFT)) & GTMDI_TBU1_WPC1_HEN1_MASK) 1750 1751 #define GTMDI_TBU1_WPC1_TSS1_MASK (0x30000000U) 1752 #define GTMDI_TBU1_WPC1_TSS1_SHIFT (28U) 1753 #define GTMDI_TBU1_WPC1_TSS1_WIDTH (2U) 1754 #define GTMDI_TBU1_WPC1_TSS1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU1_WPC1_TSS1_SHIFT)) & GTMDI_TBU1_WPC1_TSS1_MASK) 1755 /*! @} */ 1756 1757 /*! @name TBU1_WPC2 - TBUn Watchpoint Control 2 */ 1758 /*! @{ */ 1759 1760 #define GTMDI_TBU1_WPC2_SEN2_MASK (0x1U) 1761 #define GTMDI_TBU1_WPC2_SEN2_SHIFT (0U) 1762 #define GTMDI_TBU1_WPC2_SEN2_WIDTH (1U) 1763 #define GTMDI_TBU1_WPC2_SEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU1_WPC2_SEN2_SHIFT)) & GTMDI_TBU1_WPC2_SEN2_MASK) 1764 1765 #define GTMDI_TBU1_WPC2_TEN2_MASK (0x2U) 1766 #define GTMDI_TBU1_WPC2_TEN2_SHIFT (1U) 1767 #define GTMDI_TBU1_WPC2_TEN2_WIDTH (1U) 1768 #define GTMDI_TBU1_WPC2_TEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU1_WPC2_TEN2_SHIFT)) & GTMDI_TBU1_WPC2_TEN2_MASK) 1769 1770 #define GTMDI_TBU1_WPC2_STSEL2_MASK (0x30U) 1771 #define GTMDI_TBU1_WPC2_STSEL2_SHIFT (4U) 1772 #define GTMDI_TBU1_WPC2_STSEL2_WIDTH (2U) 1773 #define GTMDI_TBU1_WPC2_STSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU1_WPC2_STSEL2_SHIFT)) & GTMDI_TBU1_WPC2_STSEL2_MASK) 1774 1775 #define GTMDI_TBU1_WPC2_WTSEL2_MASK (0x7000U) 1776 #define GTMDI_TBU1_WPC2_WTSEL2_SHIFT (12U) 1777 #define GTMDI_TBU1_WPC2_WTSEL2_WIDTH (3U) 1778 #define GTMDI_TBU1_WPC2_WTSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU1_WPC2_WTSEL2_SHIFT)) & GTMDI_TBU1_WPC2_WTSEL2_MASK) 1779 1780 #define GTMDI_TBU1_WPC2_SEN1_MASK (0x10000U) 1781 #define GTMDI_TBU1_WPC2_SEN1_SHIFT (16U) 1782 #define GTMDI_TBU1_WPC2_SEN1_WIDTH (1U) 1783 #define GTMDI_TBU1_WPC2_SEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU1_WPC2_SEN1_SHIFT)) & GTMDI_TBU1_WPC2_SEN1_MASK) 1784 1785 #define GTMDI_TBU1_WPC2_TEN1_MASK (0x20000U) 1786 #define GTMDI_TBU1_WPC2_TEN1_SHIFT (17U) 1787 #define GTMDI_TBU1_WPC2_TEN1_WIDTH (1U) 1788 #define GTMDI_TBU1_WPC2_TEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU1_WPC2_TEN1_SHIFT)) & GTMDI_TBU1_WPC2_TEN1_MASK) 1789 1790 #define GTMDI_TBU1_WPC2_STSEL1_MASK (0x300000U) 1791 #define GTMDI_TBU1_WPC2_STSEL1_SHIFT (20U) 1792 #define GTMDI_TBU1_WPC2_STSEL1_WIDTH (2U) 1793 #define GTMDI_TBU1_WPC2_STSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU1_WPC2_STSEL1_SHIFT)) & GTMDI_TBU1_WPC2_STSEL1_MASK) 1794 1795 #define GTMDI_TBU1_WPC2_WTSEL1_MASK (0x70000000U) 1796 #define GTMDI_TBU1_WPC2_WTSEL1_SHIFT (28U) 1797 #define GTMDI_TBU1_WPC2_WTSEL1_WIDTH (3U) 1798 #define GTMDI_TBU1_WPC2_WTSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU1_WPC2_WTSEL1_SHIFT)) & GTMDI_TBU1_WPC2_WTSEL1_MASK) 1799 /*! @} */ 1800 1801 /*! @name TBU1_D - TBUn Watchpoint DATA */ 1802 /*! @{ */ 1803 1804 #define GTMDI_TBU1_D_TBUn_DATA_MASK (0xFFFFFFU) 1805 #define GTMDI_TBU1_D_TBUn_DATA_SHIFT (0U) 1806 #define GTMDI_TBU1_D_TBUn_DATA_WIDTH (24U) 1807 #define GTMDI_TBU1_D_TBUn_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU1_D_TBUn_DATA_SHIFT)) & GTMDI_TBU1_D_TBUn_DATA_MASK) 1808 /*! @} */ 1809 1810 /*! @name TBU2_WPC1 - TBUn Watchpoint Control 1 */ 1811 /*! @{ */ 1812 1813 #define GTMDI_TBU2_WPC1_WMC2_MASK (0x40U) 1814 #define GTMDI_TBU2_WPC1_WMC2_SHIFT (6U) 1815 #define GTMDI_TBU2_WPC1_WMC2_WIDTH (1U) 1816 #define GTMDI_TBU2_WPC1_WMC2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU2_WPC1_WMC2_SHIFT)) & GTMDI_TBU2_WPC1_WMC2_MASK) 1817 1818 #define GTMDI_TBU2_WPC1_HEN2_MASK (0x80U) 1819 #define GTMDI_TBU2_WPC1_HEN2_SHIFT (7U) 1820 #define GTMDI_TBU2_WPC1_HEN2_WIDTH (1U) 1821 #define GTMDI_TBU2_WPC1_HEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU2_WPC1_HEN2_SHIFT)) & GTMDI_TBU2_WPC1_HEN2_MASK) 1822 1823 #define GTMDI_TBU2_WPC1_TSS2_MASK (0x3000U) 1824 #define GTMDI_TBU2_WPC1_TSS2_SHIFT (12U) 1825 #define GTMDI_TBU2_WPC1_TSS2_WIDTH (2U) 1826 #define GTMDI_TBU2_WPC1_TSS2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU2_WPC1_TSS2_SHIFT)) & GTMDI_TBU2_WPC1_TSS2_MASK) 1827 1828 #define GTMDI_TBU2_WPC1_WMC1_MASK (0x400000U) 1829 #define GTMDI_TBU2_WPC1_WMC1_SHIFT (22U) 1830 #define GTMDI_TBU2_WPC1_WMC1_WIDTH (1U) 1831 #define GTMDI_TBU2_WPC1_WMC1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU2_WPC1_WMC1_SHIFT)) & GTMDI_TBU2_WPC1_WMC1_MASK) 1832 1833 #define GTMDI_TBU2_WPC1_HEN1_MASK (0x800000U) 1834 #define GTMDI_TBU2_WPC1_HEN1_SHIFT (23U) 1835 #define GTMDI_TBU2_WPC1_HEN1_WIDTH (1U) 1836 #define GTMDI_TBU2_WPC1_HEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU2_WPC1_HEN1_SHIFT)) & GTMDI_TBU2_WPC1_HEN1_MASK) 1837 1838 #define GTMDI_TBU2_WPC1_TSS1_MASK (0x30000000U) 1839 #define GTMDI_TBU2_WPC1_TSS1_SHIFT (28U) 1840 #define GTMDI_TBU2_WPC1_TSS1_WIDTH (2U) 1841 #define GTMDI_TBU2_WPC1_TSS1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU2_WPC1_TSS1_SHIFT)) & GTMDI_TBU2_WPC1_TSS1_MASK) 1842 /*! @} */ 1843 1844 /*! @name TBU2_WPC2 - TBUn Watchpoint Control 2 */ 1845 /*! @{ */ 1846 1847 #define GTMDI_TBU2_WPC2_SEN2_MASK (0x1U) 1848 #define GTMDI_TBU2_WPC2_SEN2_SHIFT (0U) 1849 #define GTMDI_TBU2_WPC2_SEN2_WIDTH (1U) 1850 #define GTMDI_TBU2_WPC2_SEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU2_WPC2_SEN2_SHIFT)) & GTMDI_TBU2_WPC2_SEN2_MASK) 1851 1852 #define GTMDI_TBU2_WPC2_TEN2_MASK (0x2U) 1853 #define GTMDI_TBU2_WPC2_TEN2_SHIFT (1U) 1854 #define GTMDI_TBU2_WPC2_TEN2_WIDTH (1U) 1855 #define GTMDI_TBU2_WPC2_TEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU2_WPC2_TEN2_SHIFT)) & GTMDI_TBU2_WPC2_TEN2_MASK) 1856 1857 #define GTMDI_TBU2_WPC2_STSEL2_MASK (0x30U) 1858 #define GTMDI_TBU2_WPC2_STSEL2_SHIFT (4U) 1859 #define GTMDI_TBU2_WPC2_STSEL2_WIDTH (2U) 1860 #define GTMDI_TBU2_WPC2_STSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU2_WPC2_STSEL2_SHIFT)) & GTMDI_TBU2_WPC2_STSEL2_MASK) 1861 1862 #define GTMDI_TBU2_WPC2_WTSEL2_MASK (0x7000U) 1863 #define GTMDI_TBU2_WPC2_WTSEL2_SHIFT (12U) 1864 #define GTMDI_TBU2_WPC2_WTSEL2_WIDTH (3U) 1865 #define GTMDI_TBU2_WPC2_WTSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU2_WPC2_WTSEL2_SHIFT)) & GTMDI_TBU2_WPC2_WTSEL2_MASK) 1866 1867 #define GTMDI_TBU2_WPC2_SEN1_MASK (0x10000U) 1868 #define GTMDI_TBU2_WPC2_SEN1_SHIFT (16U) 1869 #define GTMDI_TBU2_WPC2_SEN1_WIDTH (1U) 1870 #define GTMDI_TBU2_WPC2_SEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU2_WPC2_SEN1_SHIFT)) & GTMDI_TBU2_WPC2_SEN1_MASK) 1871 1872 #define GTMDI_TBU2_WPC2_TEN1_MASK (0x20000U) 1873 #define GTMDI_TBU2_WPC2_TEN1_SHIFT (17U) 1874 #define GTMDI_TBU2_WPC2_TEN1_WIDTH (1U) 1875 #define GTMDI_TBU2_WPC2_TEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU2_WPC2_TEN1_SHIFT)) & GTMDI_TBU2_WPC2_TEN1_MASK) 1876 1877 #define GTMDI_TBU2_WPC2_STSEL1_MASK (0x300000U) 1878 #define GTMDI_TBU2_WPC2_STSEL1_SHIFT (20U) 1879 #define GTMDI_TBU2_WPC2_STSEL1_WIDTH (2U) 1880 #define GTMDI_TBU2_WPC2_STSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU2_WPC2_STSEL1_SHIFT)) & GTMDI_TBU2_WPC2_STSEL1_MASK) 1881 1882 #define GTMDI_TBU2_WPC2_WTSEL1_MASK (0x70000000U) 1883 #define GTMDI_TBU2_WPC2_WTSEL1_SHIFT (28U) 1884 #define GTMDI_TBU2_WPC2_WTSEL1_WIDTH (3U) 1885 #define GTMDI_TBU2_WPC2_WTSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU2_WPC2_WTSEL1_SHIFT)) & GTMDI_TBU2_WPC2_WTSEL1_MASK) 1886 /*! @} */ 1887 1888 /*! @name TBU2_D - TBUn Watchpoint DATA */ 1889 /*! @{ */ 1890 1891 #define GTMDI_TBU2_D_TBUn_DATA_MASK (0xFFFFFFU) 1892 #define GTMDI_TBU2_D_TBUn_DATA_SHIFT (0U) 1893 #define GTMDI_TBU2_D_TBUn_DATA_WIDTH (24U) 1894 #define GTMDI_TBU2_D_TBUn_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU2_D_TBUn_DATA_SHIFT)) & GTMDI_TBU2_D_TBUn_DATA_MASK) 1895 /*! @} */ 1896 1897 /*! @name TBU3_WPC1 - TBUn Watchpoint Control 1 */ 1898 /*! @{ */ 1899 1900 #define GTMDI_TBU3_WPC1_WMC2_MASK (0x40U) 1901 #define GTMDI_TBU3_WPC1_WMC2_SHIFT (6U) 1902 #define GTMDI_TBU3_WPC1_WMC2_WIDTH (1U) 1903 #define GTMDI_TBU3_WPC1_WMC2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU3_WPC1_WMC2_SHIFT)) & GTMDI_TBU3_WPC1_WMC2_MASK) 1904 1905 #define GTMDI_TBU3_WPC1_HEN2_MASK (0x80U) 1906 #define GTMDI_TBU3_WPC1_HEN2_SHIFT (7U) 1907 #define GTMDI_TBU3_WPC1_HEN2_WIDTH (1U) 1908 #define GTMDI_TBU3_WPC1_HEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU3_WPC1_HEN2_SHIFT)) & GTMDI_TBU3_WPC1_HEN2_MASK) 1909 1910 #define GTMDI_TBU3_WPC1_TSS2_MASK (0x3000U) 1911 #define GTMDI_TBU3_WPC1_TSS2_SHIFT (12U) 1912 #define GTMDI_TBU3_WPC1_TSS2_WIDTH (2U) 1913 #define GTMDI_TBU3_WPC1_TSS2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU3_WPC1_TSS2_SHIFT)) & GTMDI_TBU3_WPC1_TSS2_MASK) 1914 1915 #define GTMDI_TBU3_WPC1_WMC1_MASK (0x400000U) 1916 #define GTMDI_TBU3_WPC1_WMC1_SHIFT (22U) 1917 #define GTMDI_TBU3_WPC1_WMC1_WIDTH (1U) 1918 #define GTMDI_TBU3_WPC1_WMC1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU3_WPC1_WMC1_SHIFT)) & GTMDI_TBU3_WPC1_WMC1_MASK) 1919 1920 #define GTMDI_TBU3_WPC1_HEN1_MASK (0x800000U) 1921 #define GTMDI_TBU3_WPC1_HEN1_SHIFT (23U) 1922 #define GTMDI_TBU3_WPC1_HEN1_WIDTH (1U) 1923 #define GTMDI_TBU3_WPC1_HEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU3_WPC1_HEN1_SHIFT)) & GTMDI_TBU3_WPC1_HEN1_MASK) 1924 1925 #define GTMDI_TBU3_WPC1_TSS1_MASK (0x30000000U) 1926 #define GTMDI_TBU3_WPC1_TSS1_SHIFT (28U) 1927 #define GTMDI_TBU3_WPC1_TSS1_WIDTH (2U) 1928 #define GTMDI_TBU3_WPC1_TSS1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU3_WPC1_TSS1_SHIFT)) & GTMDI_TBU3_WPC1_TSS1_MASK) 1929 /*! @} */ 1930 1931 /*! @name TBU3_WPC2 - TBUn Watchpoint Control 2 */ 1932 /*! @{ */ 1933 1934 #define GTMDI_TBU3_WPC2_SEN2_MASK (0x1U) 1935 #define GTMDI_TBU3_WPC2_SEN2_SHIFT (0U) 1936 #define GTMDI_TBU3_WPC2_SEN2_WIDTH (1U) 1937 #define GTMDI_TBU3_WPC2_SEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU3_WPC2_SEN2_SHIFT)) & GTMDI_TBU3_WPC2_SEN2_MASK) 1938 1939 #define GTMDI_TBU3_WPC2_TEN2_MASK (0x2U) 1940 #define GTMDI_TBU3_WPC2_TEN2_SHIFT (1U) 1941 #define GTMDI_TBU3_WPC2_TEN2_WIDTH (1U) 1942 #define GTMDI_TBU3_WPC2_TEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU3_WPC2_TEN2_SHIFT)) & GTMDI_TBU3_WPC2_TEN2_MASK) 1943 1944 #define GTMDI_TBU3_WPC2_STSEL2_MASK (0x30U) 1945 #define GTMDI_TBU3_WPC2_STSEL2_SHIFT (4U) 1946 #define GTMDI_TBU3_WPC2_STSEL2_WIDTH (2U) 1947 #define GTMDI_TBU3_WPC2_STSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU3_WPC2_STSEL2_SHIFT)) & GTMDI_TBU3_WPC2_STSEL2_MASK) 1948 1949 #define GTMDI_TBU3_WPC2_WTSEL2_MASK (0x7000U) 1950 #define GTMDI_TBU3_WPC2_WTSEL2_SHIFT (12U) 1951 #define GTMDI_TBU3_WPC2_WTSEL2_WIDTH (3U) 1952 #define GTMDI_TBU3_WPC2_WTSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU3_WPC2_WTSEL2_SHIFT)) & GTMDI_TBU3_WPC2_WTSEL2_MASK) 1953 1954 #define GTMDI_TBU3_WPC2_SEN1_MASK (0x10000U) 1955 #define GTMDI_TBU3_WPC2_SEN1_SHIFT (16U) 1956 #define GTMDI_TBU3_WPC2_SEN1_WIDTH (1U) 1957 #define GTMDI_TBU3_WPC2_SEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU3_WPC2_SEN1_SHIFT)) & GTMDI_TBU3_WPC2_SEN1_MASK) 1958 1959 #define GTMDI_TBU3_WPC2_TEN1_MASK (0x20000U) 1960 #define GTMDI_TBU3_WPC2_TEN1_SHIFT (17U) 1961 #define GTMDI_TBU3_WPC2_TEN1_WIDTH (1U) 1962 #define GTMDI_TBU3_WPC2_TEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU3_WPC2_TEN1_SHIFT)) & GTMDI_TBU3_WPC2_TEN1_MASK) 1963 1964 #define GTMDI_TBU3_WPC2_STSEL1_MASK (0x300000U) 1965 #define GTMDI_TBU3_WPC2_STSEL1_SHIFT (20U) 1966 #define GTMDI_TBU3_WPC2_STSEL1_WIDTH (2U) 1967 #define GTMDI_TBU3_WPC2_STSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU3_WPC2_STSEL1_SHIFT)) & GTMDI_TBU3_WPC2_STSEL1_MASK) 1968 1969 #define GTMDI_TBU3_WPC2_WTSEL1_MASK (0x70000000U) 1970 #define GTMDI_TBU3_WPC2_WTSEL1_SHIFT (28U) 1971 #define GTMDI_TBU3_WPC2_WTSEL1_WIDTH (3U) 1972 #define GTMDI_TBU3_WPC2_WTSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU3_WPC2_WTSEL1_SHIFT)) & GTMDI_TBU3_WPC2_WTSEL1_MASK) 1973 /*! @} */ 1974 1975 /*! @name TBU3_D - TBUn Watchpoint DATA */ 1976 /*! @{ */ 1977 1978 #define GTMDI_TBU3_D_TBUn_DATA_MASK (0xFFFFFFU) 1979 #define GTMDI_TBU3_D_TBUn_DATA_SHIFT (0U) 1980 #define GTMDI_TBU3_D_TBUn_DATA_WIDTH (24U) 1981 #define GTMDI_TBU3_D_TBUn_DATA(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TBU3_D_TBUn_DATA_SHIFT)) & GTMDI_TBU3_D_TBUn_DATA_MASK) 1982 /*! @} */ 1983 1984 /*! @name TIO_IN_WPC1 - TIO IN watchpoint control register 1 */ 1985 /*! @{ */ 1986 1987 #define GTMDI_TIO_IN_WPC1_CHSEL2_MASK (0x7U) 1988 #define GTMDI_TIO_IN_WPC1_CHSEL2_SHIFT (0U) 1989 #define GTMDI_TIO_IN_WPC1_CHSEL2_WIDTH (3U) 1990 #define GTMDI_TIO_IN_WPC1_CHSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_IN_WPC1_CHSEL2_SHIFT)) & GTMDI_TIO_IN_WPC1_CHSEL2_MASK) 1991 1992 #define GTMDI_TIO_IN_WPC1_WMC2_MASK (0x40U) 1993 #define GTMDI_TIO_IN_WPC1_WMC2_SHIFT (6U) 1994 #define GTMDI_TIO_IN_WPC1_WMC2_WIDTH (1U) 1995 #define GTMDI_TIO_IN_WPC1_WMC2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_IN_WPC1_WMC2_SHIFT)) & GTMDI_TIO_IN_WPC1_WMC2_MASK) 1996 1997 #define GTMDI_TIO_IN_WPC1_HEN2_MASK (0x80U) 1998 #define GTMDI_TIO_IN_WPC1_HEN2_SHIFT (7U) 1999 #define GTMDI_TIO_IN_WPC1_HEN2_WIDTH (1U) 2000 #define GTMDI_TIO_IN_WPC1_HEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_IN_WPC1_HEN2_SHIFT)) & GTMDI_TIO_IN_WPC1_HEN2_MASK) 2001 2002 #define GTMDI_TIO_IN_WPC1_SSEL2_MASK (0xF00U) 2003 #define GTMDI_TIO_IN_WPC1_SSEL2_SHIFT (8U) 2004 #define GTMDI_TIO_IN_WPC1_SSEL2_WIDTH (4U) 2005 #define GTMDI_TIO_IN_WPC1_SSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_IN_WPC1_SSEL2_SHIFT)) & GTMDI_TIO_IN_WPC1_SSEL2_MASK) 2006 2007 #define GTMDI_TIO_IN_WPC1_TSS2_MASK (0x3000U) 2008 #define GTMDI_TIO_IN_WPC1_TSS2_SHIFT (12U) 2009 #define GTMDI_TIO_IN_WPC1_TSS2_WIDTH (2U) 2010 #define GTMDI_TIO_IN_WPC1_TSS2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_IN_WPC1_TSS2_SHIFT)) & GTMDI_TIO_IN_WPC1_TSS2_MASK) 2011 2012 #define GTMDI_TIO_IN_WPC1_CHSEL1_MASK (0x70000U) 2013 #define GTMDI_TIO_IN_WPC1_CHSEL1_SHIFT (16U) 2014 #define GTMDI_TIO_IN_WPC1_CHSEL1_WIDTH (3U) 2015 #define GTMDI_TIO_IN_WPC1_CHSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_IN_WPC1_CHSEL1_SHIFT)) & GTMDI_TIO_IN_WPC1_CHSEL1_MASK) 2016 2017 #define GTMDI_TIO_IN_WPC1_WMC1_MASK (0x400000U) 2018 #define GTMDI_TIO_IN_WPC1_WMC1_SHIFT (22U) 2019 #define GTMDI_TIO_IN_WPC1_WMC1_WIDTH (1U) 2020 #define GTMDI_TIO_IN_WPC1_WMC1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_IN_WPC1_WMC1_SHIFT)) & GTMDI_TIO_IN_WPC1_WMC1_MASK) 2021 2022 #define GTMDI_TIO_IN_WPC1_HEN1_MASK (0x800000U) 2023 #define GTMDI_TIO_IN_WPC1_HEN1_SHIFT (23U) 2024 #define GTMDI_TIO_IN_WPC1_HEN1_WIDTH (1U) 2025 #define GTMDI_TIO_IN_WPC1_HEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_IN_WPC1_HEN1_SHIFT)) & GTMDI_TIO_IN_WPC1_HEN1_MASK) 2026 2027 #define GTMDI_TIO_IN_WPC1_SSEL1_MASK (0xF000000U) 2028 #define GTMDI_TIO_IN_WPC1_SSEL1_SHIFT (24U) 2029 #define GTMDI_TIO_IN_WPC1_SSEL1_WIDTH (4U) 2030 #define GTMDI_TIO_IN_WPC1_SSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_IN_WPC1_SSEL1_SHIFT)) & GTMDI_TIO_IN_WPC1_SSEL1_MASK) 2031 2032 #define GTMDI_TIO_IN_WPC1_TSS1_MASK (0x30000000U) 2033 #define GTMDI_TIO_IN_WPC1_TSS1_SHIFT (28U) 2034 #define GTMDI_TIO_IN_WPC1_TSS1_WIDTH (2U) 2035 #define GTMDI_TIO_IN_WPC1_TSS1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_IN_WPC1_TSS1_SHIFT)) & GTMDI_TIO_IN_WPC1_TSS1_MASK) 2036 /*! @} */ 2037 2038 /*! @name TIO_IN_WPC2 - TIO IN watchpoint control register 2 */ 2039 /*! @{ */ 2040 2041 #define GTMDI_TIO_IN_WPC2_SEN2_MASK (0x1U) 2042 #define GTMDI_TIO_IN_WPC2_SEN2_SHIFT (0U) 2043 #define GTMDI_TIO_IN_WPC2_SEN2_WIDTH (1U) 2044 #define GTMDI_TIO_IN_WPC2_SEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_IN_WPC2_SEN2_SHIFT)) & GTMDI_TIO_IN_WPC2_SEN2_MASK) 2045 2046 #define GTMDI_TIO_IN_WPC2_TEN2_MASK (0x2U) 2047 #define GTMDI_TIO_IN_WPC2_TEN2_SHIFT (1U) 2048 #define GTMDI_TIO_IN_WPC2_TEN2_WIDTH (1U) 2049 #define GTMDI_TIO_IN_WPC2_TEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_IN_WPC2_TEN2_SHIFT)) & GTMDI_TIO_IN_WPC2_TEN2_MASK) 2050 2051 #define GTMDI_TIO_IN_WPC2_STSEL2_MASK (0x30U) 2052 #define GTMDI_TIO_IN_WPC2_STSEL2_SHIFT (4U) 2053 #define GTMDI_TIO_IN_WPC2_STSEL2_WIDTH (2U) 2054 #define GTMDI_TIO_IN_WPC2_STSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_IN_WPC2_STSEL2_SHIFT)) & GTMDI_TIO_IN_WPC2_STSEL2_MASK) 2055 2056 #define GTMDI_TIO_IN_WPC2_WTSEL2_MASK (0x7000U) 2057 #define GTMDI_TIO_IN_WPC2_WTSEL2_SHIFT (12U) 2058 #define GTMDI_TIO_IN_WPC2_WTSEL2_WIDTH (3U) 2059 #define GTMDI_TIO_IN_WPC2_WTSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_IN_WPC2_WTSEL2_SHIFT)) & GTMDI_TIO_IN_WPC2_WTSEL2_MASK) 2060 2061 #define GTMDI_TIO_IN_WPC2_SEN1_MASK (0x10000U) 2062 #define GTMDI_TIO_IN_WPC2_SEN1_SHIFT (16U) 2063 #define GTMDI_TIO_IN_WPC2_SEN1_WIDTH (1U) 2064 #define GTMDI_TIO_IN_WPC2_SEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_IN_WPC2_SEN1_SHIFT)) & GTMDI_TIO_IN_WPC2_SEN1_MASK) 2065 2066 #define GTMDI_TIO_IN_WPC2_TEN1_MASK (0x20000U) 2067 #define GTMDI_TIO_IN_WPC2_TEN1_SHIFT (17U) 2068 #define GTMDI_TIO_IN_WPC2_TEN1_WIDTH (1U) 2069 #define GTMDI_TIO_IN_WPC2_TEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_IN_WPC2_TEN1_SHIFT)) & GTMDI_TIO_IN_WPC2_TEN1_MASK) 2070 2071 #define GTMDI_TIO_IN_WPC2_STSEL1_MASK (0x300000U) 2072 #define GTMDI_TIO_IN_WPC2_STSEL1_SHIFT (20U) 2073 #define GTMDI_TIO_IN_WPC2_STSEL1_WIDTH (2U) 2074 #define GTMDI_TIO_IN_WPC2_STSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_IN_WPC2_STSEL1_SHIFT)) & GTMDI_TIO_IN_WPC2_STSEL1_MASK) 2075 2076 #define GTMDI_TIO_IN_WPC2_WTSEL1_MASK (0x70000000U) 2077 #define GTMDI_TIO_IN_WPC2_WTSEL1_SHIFT (28U) 2078 #define GTMDI_TIO_IN_WPC2_WTSEL1_WIDTH (3U) 2079 #define GTMDI_TIO_IN_WPC2_WTSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_IN_WPC2_WTSEL1_SHIFT)) & GTMDI_TIO_IN_WPC2_WTSEL1_MASK) 2080 /*! @} */ 2081 2082 /*! @name TIO_OUT_WPC1 - TIO OUT Watchpoint Control 1 */ 2083 /*! @{ */ 2084 2085 #define GTMDI_TIO_OUT_WPC1_CHSEL2_MASK (0xFU) 2086 #define GTMDI_TIO_OUT_WPC1_CHSEL2_SHIFT (0U) 2087 #define GTMDI_TIO_OUT_WPC1_CHSEL2_WIDTH (4U) 2088 #define GTMDI_TIO_OUT_WPC1_CHSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_OUT_WPC1_CHSEL2_SHIFT)) & GTMDI_TIO_OUT_WPC1_CHSEL2_MASK) 2089 2090 #define GTMDI_TIO_OUT_WPC1_WMC2_MASK (0x40U) 2091 #define GTMDI_TIO_OUT_WPC1_WMC2_SHIFT (6U) 2092 #define GTMDI_TIO_OUT_WPC1_WMC2_WIDTH (1U) 2093 #define GTMDI_TIO_OUT_WPC1_WMC2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_OUT_WPC1_WMC2_SHIFT)) & GTMDI_TIO_OUT_WPC1_WMC2_MASK) 2094 2095 #define GTMDI_TIO_OUT_WPC1_HEN2_MASK (0x80U) 2096 #define GTMDI_TIO_OUT_WPC1_HEN2_SHIFT (7U) 2097 #define GTMDI_TIO_OUT_WPC1_HEN2_WIDTH (1U) 2098 #define GTMDI_TIO_OUT_WPC1_HEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_OUT_WPC1_HEN2_SHIFT)) & GTMDI_TIO_OUT_WPC1_HEN2_MASK) 2099 2100 #define GTMDI_TIO_OUT_WPC1_SSEL2_MASK (0xF00U) 2101 #define GTMDI_TIO_OUT_WPC1_SSEL2_SHIFT (8U) 2102 #define GTMDI_TIO_OUT_WPC1_SSEL2_WIDTH (4U) 2103 #define GTMDI_TIO_OUT_WPC1_SSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_OUT_WPC1_SSEL2_SHIFT)) & GTMDI_TIO_OUT_WPC1_SSEL2_MASK) 2104 2105 #define GTMDI_TIO_OUT_WPC1_TSS2_MASK (0x3000U) 2106 #define GTMDI_TIO_OUT_WPC1_TSS2_SHIFT (12U) 2107 #define GTMDI_TIO_OUT_WPC1_TSS2_WIDTH (2U) 2108 #define GTMDI_TIO_OUT_WPC1_TSS2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_OUT_WPC1_TSS2_SHIFT)) & GTMDI_TIO_OUT_WPC1_TSS2_MASK) 2109 2110 #define GTMDI_TIO_OUT_WPC1_POL2_MASK (0x8000U) 2111 #define GTMDI_TIO_OUT_WPC1_POL2_SHIFT (15U) 2112 #define GTMDI_TIO_OUT_WPC1_POL2_WIDTH (1U) 2113 #define GTMDI_TIO_OUT_WPC1_POL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_OUT_WPC1_POL2_SHIFT)) & GTMDI_TIO_OUT_WPC1_POL2_MASK) 2114 2115 #define GTMDI_TIO_OUT_WPC1_CHSEL1_MASK (0xF0000U) 2116 #define GTMDI_TIO_OUT_WPC1_CHSEL1_SHIFT (16U) 2117 #define GTMDI_TIO_OUT_WPC1_CHSEL1_WIDTH (4U) 2118 #define GTMDI_TIO_OUT_WPC1_CHSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_OUT_WPC1_CHSEL1_SHIFT)) & GTMDI_TIO_OUT_WPC1_CHSEL1_MASK) 2119 2120 #define GTMDI_TIO_OUT_WPC1_WMC1_MASK (0x400000U) 2121 #define GTMDI_TIO_OUT_WPC1_WMC1_SHIFT (22U) 2122 #define GTMDI_TIO_OUT_WPC1_WMC1_WIDTH (1U) 2123 #define GTMDI_TIO_OUT_WPC1_WMC1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_OUT_WPC1_WMC1_SHIFT)) & GTMDI_TIO_OUT_WPC1_WMC1_MASK) 2124 2125 #define GTMDI_TIO_OUT_WPC1_HEN1_MASK (0x800000U) 2126 #define GTMDI_TIO_OUT_WPC1_HEN1_SHIFT (23U) 2127 #define GTMDI_TIO_OUT_WPC1_HEN1_WIDTH (1U) 2128 #define GTMDI_TIO_OUT_WPC1_HEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_OUT_WPC1_HEN1_SHIFT)) & GTMDI_TIO_OUT_WPC1_HEN1_MASK) 2129 2130 #define GTMDI_TIO_OUT_WPC1_SSEL1_MASK (0xF000000U) 2131 #define GTMDI_TIO_OUT_WPC1_SSEL1_SHIFT (24U) 2132 #define GTMDI_TIO_OUT_WPC1_SSEL1_WIDTH (4U) 2133 #define GTMDI_TIO_OUT_WPC1_SSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_OUT_WPC1_SSEL1_SHIFT)) & GTMDI_TIO_OUT_WPC1_SSEL1_MASK) 2134 2135 #define GTMDI_TIO_OUT_WPC1_TSS1_MASK (0x30000000U) 2136 #define GTMDI_TIO_OUT_WPC1_TSS1_SHIFT (28U) 2137 #define GTMDI_TIO_OUT_WPC1_TSS1_WIDTH (2U) 2138 #define GTMDI_TIO_OUT_WPC1_TSS1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_OUT_WPC1_TSS1_SHIFT)) & GTMDI_TIO_OUT_WPC1_TSS1_MASK) 2139 2140 #define GTMDI_TIO_OUT_WPC1_POL1_MASK (0x80000000U) 2141 #define GTMDI_TIO_OUT_WPC1_POL1_SHIFT (31U) 2142 #define GTMDI_TIO_OUT_WPC1_POL1_WIDTH (1U) 2143 #define GTMDI_TIO_OUT_WPC1_POL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_OUT_WPC1_POL1_SHIFT)) & GTMDI_TIO_OUT_WPC1_POL1_MASK) 2144 /*! @} */ 2145 2146 /*! @name TIO_OUT_WPC2 - TIO OUT Watchpoint Control 2 */ 2147 /*! @{ */ 2148 2149 #define GTMDI_TIO_OUT_WPC2_SEN2_MASK (0x1U) 2150 #define GTMDI_TIO_OUT_WPC2_SEN2_SHIFT (0U) 2151 #define GTMDI_TIO_OUT_WPC2_SEN2_WIDTH (1U) 2152 #define GTMDI_TIO_OUT_WPC2_SEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_OUT_WPC2_SEN2_SHIFT)) & GTMDI_TIO_OUT_WPC2_SEN2_MASK) 2153 2154 #define GTMDI_TIO_OUT_WPC2_TEN2_MASK (0x2U) 2155 #define GTMDI_TIO_OUT_WPC2_TEN2_SHIFT (1U) 2156 #define GTMDI_TIO_OUT_WPC2_TEN2_WIDTH (1U) 2157 #define GTMDI_TIO_OUT_WPC2_TEN2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_OUT_WPC2_TEN2_SHIFT)) & GTMDI_TIO_OUT_WPC2_TEN2_MASK) 2158 2159 #define GTMDI_TIO_OUT_WPC2_STSEL2_MASK (0x30U) 2160 #define GTMDI_TIO_OUT_WPC2_STSEL2_SHIFT (4U) 2161 #define GTMDI_TIO_OUT_WPC2_STSEL2_WIDTH (2U) 2162 #define GTMDI_TIO_OUT_WPC2_STSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_OUT_WPC2_STSEL2_SHIFT)) & GTMDI_TIO_OUT_WPC2_STSEL2_MASK) 2163 2164 #define GTMDI_TIO_OUT_WPC2_WTSEL2_MASK (0x7000U) 2165 #define GTMDI_TIO_OUT_WPC2_WTSEL2_SHIFT (12U) 2166 #define GTMDI_TIO_OUT_WPC2_WTSEL2_WIDTH (3U) 2167 #define GTMDI_TIO_OUT_WPC2_WTSEL2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_OUT_WPC2_WTSEL2_SHIFT)) & GTMDI_TIO_OUT_WPC2_WTSEL2_MASK) 2168 2169 #define GTMDI_TIO_OUT_WPC2_SEN1_MASK (0x10000U) 2170 #define GTMDI_TIO_OUT_WPC2_SEN1_SHIFT (16U) 2171 #define GTMDI_TIO_OUT_WPC2_SEN1_WIDTH (1U) 2172 #define GTMDI_TIO_OUT_WPC2_SEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_OUT_WPC2_SEN1_SHIFT)) & GTMDI_TIO_OUT_WPC2_SEN1_MASK) 2173 2174 #define GTMDI_TIO_OUT_WPC2_TEN1_MASK (0x20000U) 2175 #define GTMDI_TIO_OUT_WPC2_TEN1_SHIFT (17U) 2176 #define GTMDI_TIO_OUT_WPC2_TEN1_WIDTH (1U) 2177 #define GTMDI_TIO_OUT_WPC2_TEN1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_OUT_WPC2_TEN1_SHIFT)) & GTMDI_TIO_OUT_WPC2_TEN1_MASK) 2178 2179 #define GTMDI_TIO_OUT_WPC2_STSEL1_MASK (0x300000U) 2180 #define GTMDI_TIO_OUT_WPC2_STSEL1_SHIFT (20U) 2181 #define GTMDI_TIO_OUT_WPC2_STSEL1_WIDTH (2U) 2182 #define GTMDI_TIO_OUT_WPC2_STSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_OUT_WPC2_STSEL1_SHIFT)) & GTMDI_TIO_OUT_WPC2_STSEL1_MASK) 2183 2184 #define GTMDI_TIO_OUT_WPC2_WTSEL1_MASK (0x70000000U) 2185 #define GTMDI_TIO_OUT_WPC2_WTSEL1_SHIFT (28U) 2186 #define GTMDI_TIO_OUT_WPC2_WTSEL1_WIDTH (3U) 2187 #define GTMDI_TIO_OUT_WPC2_WTSEL1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_TIO_OUT_WPC2_WTSEL1_SHIFT)) & GTMDI_TIO_OUT_WPC2_WTSEL1_MASK) 2188 /*! @} */ 2189 2190 /*! @name ATID - ATB Bus ID Control */ 2191 /*! @{ */ 2192 2193 #define GTMDI_ATID_ATID_MASK (0x7FU) 2194 #define GTMDI_ATID_ATID_SHIFT (0U) 2195 #define GTMDI_ATID_ATID_WIDTH (7U) 2196 #define GTMDI_ATID_ATID(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_ATID_ATID_SHIFT)) & GTMDI_ATID_ATID_MASK) 2197 /*! @} */ 2198 2199 /*! @name DEVARCH - Device Architecture */ 2200 /*! @{ */ 2201 2202 #define GTMDI_DEVARCH_ARCHID_MASK (0xFFFFU) 2203 #define GTMDI_DEVARCH_ARCHID_SHIFT (0U) 2204 #define GTMDI_DEVARCH_ARCHID_WIDTH (16U) 2205 #define GTMDI_DEVARCH_ARCHID(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DEVARCH_ARCHID_SHIFT)) & GTMDI_DEVARCH_ARCHID_MASK) 2206 2207 #define GTMDI_DEVARCH_ARCHREV_MASK (0xF0000U) 2208 #define GTMDI_DEVARCH_ARCHREV_SHIFT (16U) 2209 #define GTMDI_DEVARCH_ARCHREV_WIDTH (4U) 2210 #define GTMDI_DEVARCH_ARCHREV(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DEVARCH_ARCHREV_SHIFT)) & GTMDI_DEVARCH_ARCHREV_MASK) 2211 2212 #define GTMDI_DEVARCH_PRESENT_MASK (0x100000U) 2213 #define GTMDI_DEVARCH_PRESENT_SHIFT (20U) 2214 #define GTMDI_DEVARCH_PRESENT_WIDTH (1U) 2215 #define GTMDI_DEVARCH_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DEVARCH_PRESENT_SHIFT)) & GTMDI_DEVARCH_PRESENT_MASK) 2216 2217 #define GTMDI_DEVARCH_ARCHITECT1_MASK (0xFE00000U) 2218 #define GTMDI_DEVARCH_ARCHITECT1_SHIFT (21U) 2219 #define GTMDI_DEVARCH_ARCHITECT1_WIDTH (7U) 2220 #define GTMDI_DEVARCH_ARCHITECT1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DEVARCH_ARCHITECT1_SHIFT)) & GTMDI_DEVARCH_ARCHITECT1_MASK) 2221 2222 #define GTMDI_DEVARCH_ARCHITECT2_MASK (0xF0000000U) 2223 #define GTMDI_DEVARCH_ARCHITECT2_SHIFT (28U) 2224 #define GTMDI_DEVARCH_ARCHITECT2_WIDTH (4U) 2225 #define GTMDI_DEVARCH_ARCHITECT2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DEVARCH_ARCHITECT2_SHIFT)) & GTMDI_DEVARCH_ARCHITECT2_MASK) 2226 /*! @} */ 2227 2228 /*! @name DEVTYPE - Device Type Identifier */ 2229 /*! @{ */ 2230 2231 #define GTMDI_DEVTYPE_MAJOR_MASK (0xFU) 2232 #define GTMDI_DEVTYPE_MAJOR_SHIFT (0U) 2233 #define GTMDI_DEVTYPE_MAJOR_WIDTH (4U) 2234 #define GTMDI_DEVTYPE_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DEVTYPE_MAJOR_SHIFT)) & GTMDI_DEVTYPE_MAJOR_MASK) 2235 2236 #define GTMDI_DEVTYPE_SUB_MASK (0xF0U) 2237 #define GTMDI_DEVTYPE_SUB_SHIFT (4U) 2238 #define GTMDI_DEVTYPE_SUB_WIDTH (4U) 2239 #define GTMDI_DEVTYPE_SUB(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_DEVTYPE_SUB_SHIFT)) & GTMDI_DEVTYPE_SUB_MASK) 2240 /*! @} */ 2241 2242 /*! @name PIDR4 - Peripheral Identification 4 */ 2243 /*! @{ */ 2244 2245 #define GTMDI_PIDR4_DES_2_MASK (0xFU) 2246 #define GTMDI_PIDR4_DES_2_SHIFT (0U) 2247 #define GTMDI_PIDR4_DES_2_WIDTH (4U) 2248 #define GTMDI_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_PIDR4_DES_2_SHIFT)) & GTMDI_PIDR4_DES_2_MASK) 2249 2250 #define GTMDI_PIDR4_SIZE_MASK (0xF0U) 2251 #define GTMDI_PIDR4_SIZE_SHIFT (4U) 2252 #define GTMDI_PIDR4_SIZE_WIDTH (4U) 2253 #define GTMDI_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_PIDR4_SIZE_SHIFT)) & GTMDI_PIDR4_SIZE_MASK) 2254 /*! @} */ 2255 2256 /*! @name PIDR0 - Peripheral Identification 0 */ 2257 /*! @{ */ 2258 2259 #define GTMDI_PIDR0_PART_0_MASK (0xFFU) 2260 #define GTMDI_PIDR0_PART_0_SHIFT (0U) 2261 #define GTMDI_PIDR0_PART_0_WIDTH (8U) 2262 #define GTMDI_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_PIDR0_PART_0_SHIFT)) & GTMDI_PIDR0_PART_0_MASK) 2263 /*! @} */ 2264 2265 /*! @name PIDR1 - Peripheral Identification 1 */ 2266 /*! @{ */ 2267 2268 #define GTMDI_PIDR1_PART_1_MASK (0xFU) 2269 #define GTMDI_PIDR1_PART_1_SHIFT (0U) 2270 #define GTMDI_PIDR1_PART_1_WIDTH (4U) 2271 #define GTMDI_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_PIDR1_PART_1_SHIFT)) & GTMDI_PIDR1_PART_1_MASK) 2272 2273 #define GTMDI_PIDR1_DES_0_MASK (0xF0U) 2274 #define GTMDI_PIDR1_DES_0_SHIFT (4U) 2275 #define GTMDI_PIDR1_DES_0_WIDTH (4U) 2276 #define GTMDI_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_PIDR1_DES_0_SHIFT)) & GTMDI_PIDR1_DES_0_MASK) 2277 /*! @} */ 2278 2279 /*! @name PIDR2 - Peripheral Identification 2 */ 2280 /*! @{ */ 2281 2282 #define GTMDI_PIDR2_DES_1_MASK (0x7U) 2283 #define GTMDI_PIDR2_DES_1_SHIFT (0U) 2284 #define GTMDI_PIDR2_DES_1_WIDTH (3U) 2285 #define GTMDI_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_PIDR2_DES_1_SHIFT)) & GTMDI_PIDR2_DES_1_MASK) 2286 2287 #define GTMDI_PIDR2_JEDEC_MASK (0x8U) 2288 #define GTMDI_PIDR2_JEDEC_SHIFT (3U) 2289 #define GTMDI_PIDR2_JEDEC_WIDTH (1U) 2290 #define GTMDI_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_PIDR2_JEDEC_SHIFT)) & GTMDI_PIDR2_JEDEC_MASK) 2291 2292 #define GTMDI_PIDR2_Revision_MASK (0xF0U) 2293 #define GTMDI_PIDR2_Revision_SHIFT (4U) 2294 #define GTMDI_PIDR2_Revision_WIDTH (4U) 2295 #define GTMDI_PIDR2_Revision(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_PIDR2_Revision_SHIFT)) & GTMDI_PIDR2_Revision_MASK) 2296 /*! @} */ 2297 2298 /*! @name PIDR3 - Peripheral Identification 3 */ 2299 /*! @{ */ 2300 2301 #define GTMDI_PIDR3_CMOD_MASK (0xFU) 2302 #define GTMDI_PIDR3_CMOD_SHIFT (0U) 2303 #define GTMDI_PIDR3_CMOD_WIDTH (4U) 2304 #define GTMDI_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_PIDR3_CMOD_SHIFT)) & GTMDI_PIDR3_CMOD_MASK) 2305 2306 #define GTMDI_PIDR3_REVAND_MASK (0xF0U) 2307 #define GTMDI_PIDR3_REVAND_SHIFT (4U) 2308 #define GTMDI_PIDR3_REVAND_WIDTH (4U) 2309 #define GTMDI_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_PIDR3_REVAND_SHIFT)) & GTMDI_PIDR3_REVAND_MASK) 2310 /*! @} */ 2311 2312 /*! @name CIDR0 - Component Identification 0 */ 2313 /*! @{ */ 2314 2315 #define GTMDI_CIDR0_PRMBL_1_MASK (0xFFU) 2316 #define GTMDI_CIDR0_PRMBL_1_SHIFT (0U) 2317 #define GTMDI_CIDR0_PRMBL_1_WIDTH (8U) 2318 #define GTMDI_CIDR0_PRMBL_1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_CIDR0_PRMBL_1_SHIFT)) & GTMDI_CIDR0_PRMBL_1_MASK) 2319 /*! @} */ 2320 2321 /*! @name CIDR1 - Component Identification 1 */ 2322 /*! @{ */ 2323 2324 #define GTMDI_CIDR1_PRMBL_1_MASK (0xFU) 2325 #define GTMDI_CIDR1_PRMBL_1_SHIFT (0U) 2326 #define GTMDI_CIDR1_PRMBL_1_WIDTH (4U) 2327 #define GTMDI_CIDR1_PRMBL_1(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_CIDR1_PRMBL_1_SHIFT)) & GTMDI_CIDR1_PRMBL_1_MASK) 2328 2329 #define GTMDI_CIDR1_Class_MASK (0xF0U) 2330 #define GTMDI_CIDR1_Class_SHIFT (4U) 2331 #define GTMDI_CIDR1_Class_WIDTH (4U) 2332 #define GTMDI_CIDR1_Class(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_CIDR1_Class_SHIFT)) & GTMDI_CIDR1_Class_MASK) 2333 /*! @} */ 2334 2335 /*! @name CIDR2 - Component Identification 2 */ 2336 /*! @{ */ 2337 2338 #define GTMDI_CIDR2_PRMBL_2_MASK (0xFFU) 2339 #define GTMDI_CIDR2_PRMBL_2_SHIFT (0U) 2340 #define GTMDI_CIDR2_PRMBL_2_WIDTH (8U) 2341 #define GTMDI_CIDR2_PRMBL_2(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_CIDR2_PRMBL_2_SHIFT)) & GTMDI_CIDR2_PRMBL_2_MASK) 2342 /*! @} */ 2343 2344 /*! @name CIDR3 - Component Identification 3 */ 2345 /*! @{ */ 2346 2347 #define GTMDI_CIDR3_PRMBL_3_MASK (0xFFU) 2348 #define GTMDI_CIDR3_PRMBL_3_SHIFT (0U) 2349 #define GTMDI_CIDR3_PRMBL_3_WIDTH (8U) 2350 #define GTMDI_CIDR3_PRMBL_3(x) (((uint32_t)(((uint32_t)(x)) << GTMDI_CIDR3_PRMBL_3_SHIFT)) & GTMDI_CIDR3_PRMBL_3_MASK) 2351 /*! @} */ 2352 2353 /*! 2354 * @} 2355 */ /* end of group GTMDI_Register_Masks */ 2356 2357 /*! 2358 * @} 2359 */ /* end of group GTMDI_Peripheral_Access_Layer */ 2360 2361 #endif /* #if !defined(S32Z2_GTMDI_H_) */ 2362
