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Searched refs:GPR5 (Results 1 – 25 of 62) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1010/
Dclock_config.c341 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN()
343 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN()
629 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN_400M()
631 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN_400M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1015/
Dclock_config.c358 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN()
360 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN()
663 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN_400M()
665 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN_400M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1020/
Dclock_config.c422 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN()
424 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN()
791 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN_400M()
793 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN_400M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1024/
Dclock_config.c422 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN()
424 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN()
791 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN_400M()
793 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN_400M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1040/
Dclock_config.c473 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN()
475 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN()
907 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN_600M()
909 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN_600M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkbimxrt1050/
Dclock_config.c490 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN()
492 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN()
929 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN_528M()
931 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN_528M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1160/
Dclock_config.c802 …IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5… in BOARD_BootClockRUN()
804 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK; in BOARD_BootClockRUN()
1552 …IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5… in BOARD_BootClockRUN_500M()
1554 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK; in BOARD_BootClockRUN_500M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1060/
Dclock_config.c504 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN()
506 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN()
957 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN_528M()
959 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN_528M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1064/
Dclock_config.c506 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN()
508 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN()
961 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN_528M()
963 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN_528M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkcmimxrt1060/
Dclock_config.c503 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN()
505 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN()
956 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN_528M()
958 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN_528M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkbmimxrt1060/
Dclock_config.c504 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN()
506 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN()
957 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; in BOARD_BootClockRUN_528M()
959 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; in BOARD_BootClockRUN_528M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1170/
Dclock_config.c860 …IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5… in BOARD_BootClockRUN()
862 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK; in BOARD_BootClockRUN()
1675 …IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5… in BOARD_BootClockRUN_800M()
1677 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK; in BOARD_BootClockRUN_800M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkbmimxrt1170/
Dclock_config.c860 …IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5… in BOARD_BootClockRUN()
862 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK; in BOARD_BootClockRUN()
1675 …IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5… in BOARD_BootClockRUN_800M()
1677 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK; in BOARD_BootClockRUN_800M()
/hal_nxp-latest/mcux/mcux-sdk/drivers/iee_apc/
Dfsl_iee_apc.c113 IOMUXC_LPSR_GPR->GPR5 |= endAddr & IOMUXC_LPSR_GPR_APC_ADDR_MASK; in IEE_APC_SetRegionConfig()
345 IOMUXC_LPSR_GPR->GPR5 |= IOMUXC_LPSR_GPR_GPR5_LOCK(1); in IEE_APC_LockRegionConfig()
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h23250 …__IO uint32_t GPR5; /**< GPR5 General Purpose Register, offset:… member
23276 #define IOMUXC_GPR_GPR5_REG(base) ((base)->GPR5)
34165 …__IO uint32_t GPR5; /**< SRC General Purpose Register 5, offset… member
34193 #define SRC_GPR5_REG(base) ((base)->GPR5)
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h26560 …__IO uint32_t GPR5; /**< GPR5 General Purpose Register, offset:… member
26595 #define IOMUXC_GPR_GPR5_REG(base) ((base)->GPR5)
40541 …__IO uint32_t GPR5; /**< SRC General Purpose Register 5, offset… member
40580 #define SRC_GPR5_REG(base) ((base)->GPR5)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h35051 __IO uint32_t GPR5; /**< General Purpose Register 5, offset: 0x14 */ member
48997 …__IO uint32_t GPR5; /**< SRC General Purpose Register 5, offset: 0x84… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h35049 __IO uint32_t GPR5; /**< General Purpose Register 5, offset: 0x14 */ member
48995 …__IO uint32_t GPR5; /**< SRC General Purpose Register 5, offset: 0x84… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h35049 __IO uint32_t GPR5; /**< General Purpose Register 5, offset: 0x14 */ member
48995 …__IO uint32_t GPR5; /**< SRC General Purpose Register 5, offset: 0x84… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h35051 __IO uint32_t GPR5; /**< General Purpose Register 5, offset: 0x14 */ member
48997 …__IO uint32_t GPR5; /**< SRC General Purpose Register 5, offset: 0x84… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h35051 __IO uint32_t GPR5; /**< General Purpose Register 5, offset: 0x14 */ member
48997 …__IO uint32_t GPR5; /**< SRC General Purpose Register 5, offset: 0x84… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_cm7.h35049 __IO uint32_t GPR5; /**< General Purpose Register 5, offset: 0x14 */ member
48995 …__IO uint32_t GPR5; /**< SRC General Purpose Register 5, offset: 0x84… member
DMIMX8MN6_ca53.h35063 __IO uint32_t GPR5; /**< General Purpose Register 5, offset: 0x14 */ member
49009 …__IO uint32_t GPR5; /**< SRC General Purpose Register 5, offset: 0x84… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h16413 …__IO uint32_t GPR5; /**< GPR5 General Purpose Register, offset: 0x14 … member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h18915 …__IO uint32_t GPR5; /**< GPR5 General Purpose Register, offset: 0x14 … member

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