1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_GPR3.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_GPR3 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_GPR3_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_GPR3_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- GPR3 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup GPR3_Peripheral_Access_Layer GPR3 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** GPR3 - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t LVFCCUGD3; /**< VFCCU Global DID register 3, offset: 0x0 */ 74 __IO uint32_t LVFCCULD9; /**< VFCCU Local DID register 9, offset: 0x4 */ 75 __IO uint32_t LVFCCULD10; /**< VFCCU Local DID register 10, offset: 0x8 */ 76 __IO uint32_t LVFCCULD11; /**< VFCCU Local DID register 11, offset: 0xC */ 77 __I uint32_t DDRCS; /**< DDRC Status, offset: 0x10 */ 78 __IO uint32_t DDRCC; /**< DDRC Control, offset: 0x14 */ 79 __IO uint32_t GENC0; /**< Generic control register 0, offset: 0x18 */ 80 uint8_t RESERVED_0[36]; 81 __IO uint32_t FUNCC6; /**< Enable for TX Ack Suppress Logic, offset: 0x40 */ 82 uint8_t RESERVED_1[12]; 83 __I uint32_t INITM3; /**< NoC Initiator NIU Timeout Status, offset: 0x50 */ 84 __I uint32_t TARGTMS3; /**< NoC Target NIU Timeout Status, offset: 0x54 */ 85 __IO uint32_t TARGTMC3; /**< NoC Target NIU Timeout Control, offset: 0x58 */ 86 __IO uint32_t RTU0FDC; /**< RTU0 Fence and Drain Control, offset: 0x5C */ 87 __I uint32_t RTU0FDS; /**< RTU0 Fence and Drain Status, offset: 0x60 */ 88 __IO uint32_t RTU1FDC; /**< RTU1 Fence and Drain Control, offset: 0x64 */ 89 __I uint32_t RTU1FDS; /**< RTU1 Fence and Drain Status, offset: 0x68 */ 90 uint8_t RESERVED_2[4]; 91 __IO uint32_t CE0RSTCNT; /**< FlexLLCE Cortex-M33 Core 0 Reset Counter, offset: 0x70 */ 92 __IO uint32_t CE1RSTCNT; /**< FlexLLCE Cortex-M33 Core 1 Reset Counter, offset: 0x74 */ 93 __IO uint32_t CLKOUT4SEL; /**< CLKOUT_4 MUX select, offset: 0x78 */ 94 __IO uint32_t RGMC; /**< MC_RGM Control, offset: 0x7C */ 95 __I uint32_t XRDC_INT_S; /**< XRDC Interrupt Source, offset: 0x80 */ 96 uint8_t RESERVED_3[32]; 97 __I uint32_t FLEXLLCECM33S; /**< FlexLLCE Cortex-M33 Core 0 Status, offset: 0xA4 */ 98 __I uint32_t FLEXLLCECM33CES; /**< FlexLLCE Cortex-M33 Core 1 Status, offset: 0xA8 */ 99 uint8_t RESERVED_4[12]; 100 __IO uint32_t XPAR3; /**< Interface parity control and status register, offset: 0xB8 */ 101 __IO uint32_t XPAR4; /**< Interface parity control and status register, offset: 0xBC */ 102 __IO uint32_t RTU0XPAR; /**< RTU0 global parity control register, offset: 0xC0 */ 103 __IO uint32_t RTU1XPAR; /**< RTU1 global parity control register, offset: 0xC4 */ 104 } GPR3_Type, *GPR3_MemMapPtr; 105 106 /** Number of instances of the GPR3 module. */ 107 #define GPR3_INSTANCE_COUNT (1u) 108 109 /* GPR3 - Peripheral instance base addresses */ 110 /** Peripheral GPR3 base address */ 111 #define IP_GPR3_BASE (0x41860000u) 112 /** Peripheral GPR3 base pointer */ 113 #define IP_GPR3 ((GPR3_Type *)IP_GPR3_BASE) 114 /** Array initializer of GPR3 peripheral base addresses */ 115 #define IP_GPR3_BASE_ADDRS { IP_GPR3_BASE } 116 /** Array initializer of GPR3 peripheral base pointers */ 117 #define IP_GPR3_BASE_PTRS { IP_GPR3 } 118 119 /* ---------------------------------------------------------------------------- 120 -- GPR3 Register Masks 121 ---------------------------------------------------------------------------- */ 122 123 /*! 124 * @addtogroup GPR3_Register_Masks GPR3 Register Masks 125 * @{ 126 */ 127 128 /*! @name LVFCCUGD3 - VFCCU Global DID register 3 */ 129 /*! @{ */ 130 131 #define GPR3_LVFCCUGD3_FHID_MASK (0xFU) 132 #define GPR3_LVFCCUGD3_FHID_SHIFT (0U) 133 #define GPR3_LVFCCUGD3_FHID_WIDTH (4U) 134 #define GPR3_LVFCCUGD3_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR3_LVFCCUGD3_FHID_SHIFT)) & GPR3_LVFCCUGD3_FHID_MASK) 135 /*! @} */ 136 137 /*! @name LVFCCULD9 - VFCCU Local DID register 9 */ 138 /*! @{ */ 139 140 #define GPR3_LVFCCULD9_FHID_MASK (0xFFFFFFFFU) 141 #define GPR3_LVFCCULD9_FHID_SHIFT (0U) 142 #define GPR3_LVFCCULD9_FHID_WIDTH (32U) 143 #define GPR3_LVFCCULD9_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR3_LVFCCULD9_FHID_SHIFT)) & GPR3_LVFCCULD9_FHID_MASK) 144 /*! @} */ 145 146 /*! @name LVFCCULD10 - VFCCU Local DID register 10 */ 147 /*! @{ */ 148 149 #define GPR3_LVFCCULD10_FHID_MASK (0xFFFFFFFFU) 150 #define GPR3_LVFCCULD10_FHID_SHIFT (0U) 151 #define GPR3_LVFCCULD10_FHID_WIDTH (32U) 152 #define GPR3_LVFCCULD10_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR3_LVFCCULD10_FHID_SHIFT)) & GPR3_LVFCCULD10_FHID_MASK) 153 /*! @} */ 154 155 /*! @name LVFCCULD11 - VFCCU Local DID register 11 */ 156 /*! @{ */ 157 158 #define GPR3_LVFCCULD11_FHID_MASK (0xFFFFFFFFU) 159 #define GPR3_LVFCCULD11_FHID_SHIFT (0U) 160 #define GPR3_LVFCCULD11_FHID_WIDTH (32U) 161 #define GPR3_LVFCCULD11_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR3_LVFCCULD11_FHID_SHIFT)) & GPR3_LVFCCULD11_FHID_MASK) 162 /*! @} */ 163 164 /*! @name DDRCS - DDRC Status */ 165 /*! @{ */ 166 167 #define GPR3_DDRCS_RCMC_MASK (0x1U) 168 #define GPR3_DDRCS_RCMC_SHIFT (0U) 169 #define GPR3_DDRCS_RCMC_WIDTH (1U) 170 #define GPR3_DDRCS_RCMC(x) (((uint32_t)(((uint32_t)(x)) << GPR3_DDRCS_RCMC_SHIFT)) & GPR3_DDRCS_RCMC_MASK) 171 /*! @} */ 172 173 /*! @name DDRCC - DDRC Control */ 174 /*! @{ */ 175 176 #define GPR3_DDRCC_CMR_MASK (0x1U) 177 #define GPR3_DDRCC_CMR_SHIFT (0U) 178 #define GPR3_DDRCC_CMR_WIDTH (1U) 179 #define GPR3_DDRCC_CMR(x) (((uint32_t)(((uint32_t)(x)) << GPR3_DDRCC_CMR_SHIFT)) & GPR3_DDRCC_CMR_MASK) 180 181 #define GPR3_DDRCC_DSRR_MASK (0x2U) 182 #define GPR3_DDRCC_DSRR_SHIFT (1U) 183 #define GPR3_DDRCC_DSRR_WIDTH (1U) 184 #define GPR3_DDRCC_DSRR(x) (((uint32_t)(((uint32_t)(x)) << GPR3_DDRCC_DSRR_SHIFT)) & GPR3_DDRCC_DSRR_MASK) 185 /*! @} */ 186 187 /*! @name GENC0 - Generic control register 0 */ 188 /*! @{ */ 189 190 #define GPR3_GENC0_CTRL0_MASK (0xFFFFFFFFU) 191 #define GPR3_GENC0_CTRL0_SHIFT (0U) 192 #define GPR3_GENC0_CTRL0_WIDTH (32U) 193 #define GPR3_GENC0_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << GPR3_GENC0_CTRL0_SHIFT)) & GPR3_GENC0_CTRL0_MASK) 194 /*! @} */ 195 196 /*! @name FUNCC6 - Enable for TX Ack Suppress Logic */ 197 /*! @{ */ 198 199 #define GPR3_FUNCC6_CTRL_MASK (0xFFFFFFFFU) 200 #define GPR3_FUNCC6_CTRL_SHIFT (0U) 201 #define GPR3_FUNCC6_CTRL_WIDTH (32U) 202 #define GPR3_FUNCC6_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GPR3_FUNCC6_CTRL_SHIFT)) & GPR3_FUNCC6_CTRL_MASK) 203 /*! @} */ 204 205 /*! @name INITM3 - NoC Initiator NIU Timeout Status */ 206 /*! @{ */ 207 208 #define GPR3_INITM3_STAT_MASK (0xFFFFFFFFU) 209 #define GPR3_INITM3_STAT_SHIFT (0U) 210 #define GPR3_INITM3_STAT_WIDTH (32U) 211 #define GPR3_INITM3_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPR3_INITM3_STAT_SHIFT)) & GPR3_INITM3_STAT_MASK) 212 /*! @} */ 213 214 /*! @name TARGTMS3 - NoC Target NIU Timeout Status */ 215 /*! @{ */ 216 217 #define GPR3_TARGTMS3_STAT_MASK (0xFFFFFFFFU) 218 #define GPR3_TARGTMS3_STAT_SHIFT (0U) 219 #define GPR3_TARGTMS3_STAT_WIDTH (32U) 220 #define GPR3_TARGTMS3_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPR3_TARGTMS3_STAT_SHIFT)) & GPR3_TARGTMS3_STAT_MASK) 221 /*! @} */ 222 223 /*! @name TARGTMC3 - NoC Target NIU Timeout Control */ 224 /*! @{ */ 225 226 #define GPR3_TARGTMC3_EN_MASK (0xFFFFFFFFU) 227 #define GPR3_TARGTMC3_EN_SHIFT (0U) 228 #define GPR3_TARGTMC3_EN_WIDTH (32U) 229 #define GPR3_TARGTMC3_EN(x) (((uint32_t)(((uint32_t)(x)) << GPR3_TARGTMC3_EN_SHIFT)) & GPR3_TARGTMC3_EN_MASK) 230 /*! @} */ 231 232 /*! @name RTU0FDC - RTU0 Fence and Drain Control */ 233 /*! @{ */ 234 235 #define GPR3_RTU0FDC_FDREQ_SYS_NOC_MASK (0x1U) 236 #define GPR3_RTU0FDC_FDREQ_SYS_NOC_SHIFT (0U) 237 #define GPR3_RTU0FDC_FDREQ_SYS_NOC_WIDTH (1U) 238 #define GPR3_RTU0FDC_FDREQ_SYS_NOC(x) (((uint32_t)(((uint32_t)(x)) << GPR3_RTU0FDC_FDREQ_SYS_NOC_SHIFT)) & GPR3_RTU0FDC_FDREQ_SYS_NOC_MASK) 239 240 #define GPR3_RTU0FDC_FDREQ_LLC_MASK (0x2U) 241 #define GPR3_RTU0FDC_FDREQ_LLC_SHIFT (1U) 242 #define GPR3_RTU0FDC_FDREQ_LLC_WIDTH (1U) 243 #define GPR3_RTU0FDC_FDREQ_LLC(x) (((uint32_t)(((uint32_t)(x)) << GPR3_RTU0FDC_FDREQ_LLC_SHIFT)) & GPR3_RTU0FDC_FDREQ_LLC_MASK) 244 245 #define GPR3_RTU0FDC_SRAM_KILL_ACCESS_MASK (0x4U) 246 #define GPR3_RTU0FDC_SRAM_KILL_ACCESS_SHIFT (2U) 247 #define GPR3_RTU0FDC_SRAM_KILL_ACCESS_WIDTH (1U) 248 #define GPR3_RTU0FDC_SRAM_KILL_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << GPR3_RTU0FDC_SRAM_KILL_ACCESS_SHIFT)) & GPR3_RTU0FDC_SRAM_KILL_ACCESS_MASK) 249 /*! @} */ 250 251 /*! @name RTU0FDS - RTU0 Fence and Drain Status */ 252 /*! @{ */ 253 254 #define GPR3_RTU0FDS_IDLE_SYS_NOC_MASK (0x1U) 255 #define GPR3_RTU0FDS_IDLE_SYS_NOC_SHIFT (0U) 256 #define GPR3_RTU0FDS_IDLE_SYS_NOC_WIDTH (1U) 257 #define GPR3_RTU0FDS_IDLE_SYS_NOC(x) (((uint32_t)(((uint32_t)(x)) << GPR3_RTU0FDS_IDLE_SYS_NOC_SHIFT)) & GPR3_RTU0FDS_IDLE_SYS_NOC_MASK) 258 259 #define GPR3_RTU0FDS_IDLE_LLC_MASK (0x2U) 260 #define GPR3_RTU0FDS_IDLE_LLC_SHIFT (1U) 261 #define GPR3_RTU0FDS_IDLE_LLC_WIDTH (1U) 262 #define GPR3_RTU0FDS_IDLE_LLC(x) (((uint32_t)(((uint32_t)(x)) << GPR3_RTU0FDS_IDLE_LLC_SHIFT)) & GPR3_RTU0FDS_IDLE_LLC_MASK) 263 /*! @} */ 264 265 /*! @name RTU1FDC - RTU1 Fence and Drain Control */ 266 /*! @{ */ 267 268 #define GPR3_RTU1FDC_FDREQ_SYS_NOC_MASK (0x1U) 269 #define GPR3_RTU1FDC_FDREQ_SYS_NOC_SHIFT (0U) 270 #define GPR3_RTU1FDC_FDREQ_SYS_NOC_WIDTH (1U) 271 #define GPR3_RTU1FDC_FDREQ_SYS_NOC(x) (((uint32_t)(((uint32_t)(x)) << GPR3_RTU1FDC_FDREQ_SYS_NOC_SHIFT)) & GPR3_RTU1FDC_FDREQ_SYS_NOC_MASK) 272 273 #define GPR3_RTU1FDC_FDREQ_LLC_MASK (0x2U) 274 #define GPR3_RTU1FDC_FDREQ_LLC_SHIFT (1U) 275 #define GPR3_RTU1FDC_FDREQ_LLC_WIDTH (1U) 276 #define GPR3_RTU1FDC_FDREQ_LLC(x) (((uint32_t)(((uint32_t)(x)) << GPR3_RTU1FDC_FDREQ_LLC_SHIFT)) & GPR3_RTU1FDC_FDREQ_LLC_MASK) 277 278 #define GPR3_RTU1FDC_SRAM_KILL_ACCESS_MASK (0x4U) 279 #define GPR3_RTU1FDC_SRAM_KILL_ACCESS_SHIFT (2U) 280 #define GPR3_RTU1FDC_SRAM_KILL_ACCESS_WIDTH (1U) 281 #define GPR3_RTU1FDC_SRAM_KILL_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << GPR3_RTU1FDC_SRAM_KILL_ACCESS_SHIFT)) & GPR3_RTU1FDC_SRAM_KILL_ACCESS_MASK) 282 /*! @} */ 283 284 /*! @name RTU1FDS - RTU1 Fence and Drain Status */ 285 /*! @{ */ 286 287 #define GPR3_RTU1FDS_IDLE_SYS_NOC_MASK (0x1U) 288 #define GPR3_RTU1FDS_IDLE_SYS_NOC_SHIFT (0U) 289 #define GPR3_RTU1FDS_IDLE_SYS_NOC_WIDTH (1U) 290 #define GPR3_RTU1FDS_IDLE_SYS_NOC(x) (((uint32_t)(((uint32_t)(x)) << GPR3_RTU1FDS_IDLE_SYS_NOC_SHIFT)) & GPR3_RTU1FDS_IDLE_SYS_NOC_MASK) 291 292 #define GPR3_RTU1FDS_IDLE_LLC_MASK (0x2U) 293 #define GPR3_RTU1FDS_IDLE_LLC_SHIFT (1U) 294 #define GPR3_RTU1FDS_IDLE_LLC_WIDTH (1U) 295 #define GPR3_RTU1FDS_IDLE_LLC(x) (((uint32_t)(((uint32_t)(x)) << GPR3_RTU1FDS_IDLE_LLC_SHIFT)) & GPR3_RTU1FDS_IDLE_LLC_MASK) 296 /*! @} */ 297 298 /*! @name CE0RSTCNT - FlexLLCE Cortex-M33 Core 0 Reset Counter */ 299 /*! @{ */ 300 301 #define GPR3_CE0RSTCNT_CNTVAL_MASK (0x3FU) 302 #define GPR3_CE0RSTCNT_CNTVAL_SHIFT (0U) 303 #define GPR3_CE0RSTCNT_CNTVAL_WIDTH (6U) 304 #define GPR3_CE0RSTCNT_CNTVAL(x) (((uint32_t)(((uint32_t)(x)) << GPR3_CE0RSTCNT_CNTVAL_SHIFT)) & GPR3_CE0RSTCNT_CNTVAL_MASK) 305 /*! @} */ 306 307 /*! @name CE1RSTCNT - FlexLLCE Cortex-M33 Core 1 Reset Counter */ 308 /*! @{ */ 309 310 #define GPR3_CE1RSTCNT_CNTVAL_MASK (0x3FU) 311 #define GPR3_CE1RSTCNT_CNTVAL_SHIFT (0U) 312 #define GPR3_CE1RSTCNT_CNTVAL_WIDTH (6U) 313 #define GPR3_CE1RSTCNT_CNTVAL(x) (((uint32_t)(((uint32_t)(x)) << GPR3_CE1RSTCNT_CNTVAL_SHIFT)) & GPR3_CE1RSTCNT_CNTVAL_MASK) 314 /*! @} */ 315 316 /*! @name CLKOUT4SEL - CLKOUT_4 MUX select */ 317 /*! @{ */ 318 319 #define GPR3_CLKOUT4SEL_MUXSEL_MASK (0xFU) 320 #define GPR3_CLKOUT4SEL_MUXSEL_SHIFT (0U) 321 #define GPR3_CLKOUT4SEL_MUXSEL_WIDTH (4U) 322 #define GPR3_CLKOUT4SEL_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << GPR3_CLKOUT4SEL_MUXSEL_SHIFT)) & GPR3_CLKOUT4SEL_MUXSEL_MASK) 323 /*! @} */ 324 325 /*! @name RGMC - MC_RGM Control */ 326 /*! @{ */ 327 328 #define GPR3_RGMC_FUNC_RST_ENTRY_PROC_DONE_MASK (0xFFU) 329 #define GPR3_RGMC_FUNC_RST_ENTRY_PROC_DONE_SHIFT (0U) 330 #define GPR3_RGMC_FUNC_RST_ENTRY_PROC_DONE_WIDTH (8U) 331 #define GPR3_RGMC_FUNC_RST_ENTRY_PROC_DONE(x) (((uint32_t)(((uint32_t)(x)) << GPR3_RGMC_FUNC_RST_ENTRY_PROC_DONE_SHIFT)) & GPR3_RGMC_FUNC_RST_ENTRY_PROC_DONE_MASK) 332 333 #define GPR3_RGMC_FUNC_RST_EXIT_PROC_DONE_MASK (0x300U) 334 #define GPR3_RGMC_FUNC_RST_EXIT_PROC_DONE_SHIFT (8U) 335 #define GPR3_RGMC_FUNC_RST_EXIT_PROC_DONE_WIDTH (2U) 336 #define GPR3_RGMC_FUNC_RST_EXIT_PROC_DONE(x) (((uint32_t)(((uint32_t)(x)) << GPR3_RGMC_FUNC_RST_EXIT_PROC_DONE_SHIFT)) & GPR3_RGMC_FUNC_RST_EXIT_PROC_DONE_MASK) 337 338 #define GPR3_RGMC_DEST_RST_DISABLE_MASK (0x1FFFC00U) 339 #define GPR3_RGMC_DEST_RST_DISABLE_SHIFT (10U) 340 #define GPR3_RGMC_DEST_RST_DISABLE_WIDTH (15U) 341 #define GPR3_RGMC_DEST_RST_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPR3_RGMC_DEST_RST_DISABLE_SHIFT)) & GPR3_RGMC_DEST_RST_DISABLE_MASK) 342 /*! @} */ 343 344 /*! @name XRDC_INT_S - XRDC Interrupt Source */ 345 /*! @{ */ 346 347 #define GPR3_XRDC_INT_S_XRDC_INT_SRC_MASK (0x7FFU) 348 #define GPR3_XRDC_INT_S_XRDC_INT_SRC_SHIFT (0U) 349 #define GPR3_XRDC_INT_S_XRDC_INT_SRC_WIDTH (11U) 350 #define GPR3_XRDC_INT_S_XRDC_INT_SRC(x) (((uint32_t)(((uint32_t)(x)) << GPR3_XRDC_INT_S_XRDC_INT_SRC_SHIFT)) & GPR3_XRDC_INT_S_XRDC_INT_SRC_MASK) 351 /*! @} */ 352 353 /*! @name FLEXLLCECM33S - FlexLLCE Cortex-M33 Core 0 Status */ 354 /*! @{ */ 355 356 #define GPR3_FLEXLLCECM33S_SLEEPDEEP_MASK (0x1U) 357 #define GPR3_FLEXLLCECM33S_SLEEPDEEP_SHIFT (0U) 358 #define GPR3_FLEXLLCECM33S_SLEEPDEEP_WIDTH (1U) 359 #define GPR3_FLEXLLCECM33S_SLEEPDEEP(x) (((uint32_t)(((uint32_t)(x)) << GPR3_FLEXLLCECM33S_SLEEPDEEP_SHIFT)) & GPR3_FLEXLLCECM33S_SLEEPDEEP_MASK) 360 361 #define GPR3_FLEXLLCECM33S_SLEEPHOLDAn_MASK (0x2U) 362 #define GPR3_FLEXLLCECM33S_SLEEPHOLDAn_SHIFT (1U) 363 #define GPR3_FLEXLLCECM33S_SLEEPHOLDAn_WIDTH (1U) 364 #define GPR3_FLEXLLCECM33S_SLEEPHOLDAn(x) (((uint32_t)(((uint32_t)(x)) << GPR3_FLEXLLCECM33S_SLEEPHOLDAn_SHIFT)) & GPR3_FLEXLLCECM33S_SLEEPHOLDAn_MASK) 365 366 #define GPR3_FLEXLLCECM33S_SLEEPING_MASK (0x4U) 367 #define GPR3_FLEXLLCECM33S_SLEEPING_SHIFT (2U) 368 #define GPR3_FLEXLLCECM33S_SLEEPING_WIDTH (1U) 369 #define GPR3_FLEXLLCECM33S_SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << GPR3_FLEXLLCECM33S_SLEEPING_SHIFT)) & GPR3_FLEXLLCECM33S_SLEEPING_MASK) 370 371 #define GPR3_FLEXLLCECM33S_CORECLKEN_MASK (0x8U) 372 #define GPR3_FLEXLLCECM33S_CORECLKEN_SHIFT (3U) 373 #define GPR3_FLEXLLCECM33S_CORECLKEN_WIDTH (1U) 374 #define GPR3_FLEXLLCECM33S_CORECLKEN(x) (((uint32_t)(((uint32_t)(x)) << GPR3_FLEXLLCECM33S_CORECLKEN_SHIFT)) & GPR3_FLEXLLCECM33S_CORECLKEN_MASK) 375 376 #define GPR3_FLEXLLCECM33S_INTVFETCH_MASK (0x10U) 377 #define GPR3_FLEXLLCECM33S_INTVFETCH_SHIFT (4U) 378 #define GPR3_FLEXLLCECM33S_INTVFETCH_WIDTH (1U) 379 #define GPR3_FLEXLLCECM33S_INTVFETCH(x) (((uint32_t)(((uint32_t)(x)) << GPR3_FLEXLLCECM33S_INTVFETCH_SHIFT)) & GPR3_FLEXLLCECM33S_INTVFETCH_MASK) 380 381 #define GPR3_FLEXLLCECM33S_CPULOCKUP_MASK (0x20U) 382 #define GPR3_FLEXLLCECM33S_CPULOCKUP_SHIFT (5U) 383 #define GPR3_FLEXLLCECM33S_CPULOCKUP_WIDTH (1U) 384 #define GPR3_FLEXLLCECM33S_CPULOCKUP(x) (((uint32_t)(((uint32_t)(x)) << GPR3_FLEXLLCECM33S_CPULOCKUP_SHIFT)) & GPR3_FLEXLLCECM33S_CPULOCKUP_MASK) 385 386 #define GPR3_FLEXLLCECM33S_CURRNS_MASK (0x40U) 387 #define GPR3_FLEXLLCECM33S_CURRNS_SHIFT (6U) 388 #define GPR3_FLEXLLCECM33S_CURRNS_WIDTH (1U) 389 #define GPR3_FLEXLLCECM33S_CURRNS(x) (((uint32_t)(((uint32_t)(x)) << GPR3_FLEXLLCECM33S_CURRNS_SHIFT)) & GPR3_FLEXLLCECM33S_CURRNS_MASK) 390 391 #define GPR3_FLEXLLCECM33S_SYSRSTREQ_MASK (0x80U) 392 #define GPR3_FLEXLLCECM33S_SYSRSTREQ_SHIFT (7U) 393 #define GPR3_FLEXLLCECM33S_SYSRSTREQ_WIDTH (1U) 394 #define GPR3_FLEXLLCECM33S_SYSRSTREQ(x) (((uint32_t)(((uint32_t)(x)) << GPR3_FLEXLLCECM33S_SYSRSTREQ_SHIFT)) & GPR3_FLEXLLCECM33S_SYSRSTREQ_MASK) 395 /*! @} */ 396 397 /*! @name FLEXLLCECM33CES - FlexLLCE Cortex-M33 Core 1 Status */ 398 /*! @{ */ 399 400 #define GPR3_FLEXLLCECM33CES_SLEEPDEEP_MASK (0x1U) 401 #define GPR3_FLEXLLCECM33CES_SLEEPDEEP_SHIFT (0U) 402 #define GPR3_FLEXLLCECM33CES_SLEEPDEEP_WIDTH (1U) 403 #define GPR3_FLEXLLCECM33CES_SLEEPDEEP(x) (((uint32_t)(((uint32_t)(x)) << GPR3_FLEXLLCECM33CES_SLEEPDEEP_SHIFT)) & GPR3_FLEXLLCECM33CES_SLEEPDEEP_MASK) 404 405 #define GPR3_FLEXLLCECM33CES_SLEEPHOLDAn_MASK (0x2U) 406 #define GPR3_FLEXLLCECM33CES_SLEEPHOLDAn_SHIFT (1U) 407 #define GPR3_FLEXLLCECM33CES_SLEEPHOLDAn_WIDTH (1U) 408 #define GPR3_FLEXLLCECM33CES_SLEEPHOLDAn(x) (((uint32_t)(((uint32_t)(x)) << GPR3_FLEXLLCECM33CES_SLEEPHOLDAn_SHIFT)) & GPR3_FLEXLLCECM33CES_SLEEPHOLDAn_MASK) 409 410 #define GPR3_FLEXLLCECM33CES_SLEEPING_MASK (0x4U) 411 #define GPR3_FLEXLLCECM33CES_SLEEPING_SHIFT (2U) 412 #define GPR3_FLEXLLCECM33CES_SLEEPING_WIDTH (1U) 413 #define GPR3_FLEXLLCECM33CES_SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << GPR3_FLEXLLCECM33CES_SLEEPING_SHIFT)) & GPR3_FLEXLLCECM33CES_SLEEPING_MASK) 414 415 #define GPR3_FLEXLLCECM33CES_CORECLKEN_MASK (0x8U) 416 #define GPR3_FLEXLLCECM33CES_CORECLKEN_SHIFT (3U) 417 #define GPR3_FLEXLLCECM33CES_CORECLKEN_WIDTH (1U) 418 #define GPR3_FLEXLLCECM33CES_CORECLKEN(x) (((uint32_t)(((uint32_t)(x)) << GPR3_FLEXLLCECM33CES_CORECLKEN_SHIFT)) & GPR3_FLEXLLCECM33CES_CORECLKEN_MASK) 419 420 #define GPR3_FLEXLLCECM33CES_INTVFETCH_MASK (0x10U) 421 #define GPR3_FLEXLLCECM33CES_INTVFETCH_SHIFT (4U) 422 #define GPR3_FLEXLLCECM33CES_INTVFETCH_WIDTH (1U) 423 #define GPR3_FLEXLLCECM33CES_INTVFETCH(x) (((uint32_t)(((uint32_t)(x)) << GPR3_FLEXLLCECM33CES_INTVFETCH_SHIFT)) & GPR3_FLEXLLCECM33CES_INTVFETCH_MASK) 424 425 #define GPR3_FLEXLLCECM33CES_CPULOCKUP_MASK (0x20U) 426 #define GPR3_FLEXLLCECM33CES_CPULOCKUP_SHIFT (5U) 427 #define GPR3_FLEXLLCECM33CES_CPULOCKUP_WIDTH (1U) 428 #define GPR3_FLEXLLCECM33CES_CPULOCKUP(x) (((uint32_t)(((uint32_t)(x)) << GPR3_FLEXLLCECM33CES_CPULOCKUP_SHIFT)) & GPR3_FLEXLLCECM33CES_CPULOCKUP_MASK) 429 430 #define GPR3_FLEXLLCECM33CES_CURRNS_MASK (0x40U) 431 #define GPR3_FLEXLLCECM33CES_CURRNS_SHIFT (6U) 432 #define GPR3_FLEXLLCECM33CES_CURRNS_WIDTH (1U) 433 #define GPR3_FLEXLLCECM33CES_CURRNS(x) (((uint32_t)(((uint32_t)(x)) << GPR3_FLEXLLCECM33CES_CURRNS_SHIFT)) & GPR3_FLEXLLCECM33CES_CURRNS_MASK) 434 435 #define GPR3_FLEXLLCECM33CES_SYSRSTREQ_MASK (0x80U) 436 #define GPR3_FLEXLLCECM33CES_SYSRSTREQ_SHIFT (7U) 437 #define GPR3_FLEXLLCECM33CES_SYSRSTREQ_WIDTH (1U) 438 #define GPR3_FLEXLLCECM33CES_SYSRSTREQ(x) (((uint32_t)(((uint32_t)(x)) << GPR3_FLEXLLCECM33CES_SYSRSTREQ_SHIFT)) & GPR3_FLEXLLCECM33CES_SYSRSTREQ_MASK) 439 /*! @} */ 440 441 /*! @name XPAR3 - Interface parity control and status register */ 442 /*! @{ */ 443 444 #define GPR3_XPAR3_DIS_MASK (0x3FU) 445 #define GPR3_XPAR3_DIS_SHIFT (0U) 446 #define GPR3_XPAR3_DIS_WIDTH (6U) 447 #define GPR3_XPAR3_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPR3_XPAR3_DIS_SHIFT)) & GPR3_XPAR3_DIS_MASK) 448 449 #define GPR3_XPAR3_STAT_MASK (0x3F00U) 450 #define GPR3_XPAR3_STAT_SHIFT (8U) 451 #define GPR3_XPAR3_STAT_WIDTH (6U) 452 #define GPR3_XPAR3_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPR3_XPAR3_STAT_SHIFT)) & GPR3_XPAR3_STAT_MASK) 453 /*! @} */ 454 455 /*! @name XPAR4 - Interface parity control and status register */ 456 /*! @{ */ 457 458 #define GPR3_XPAR4_DIS_MASK (0x3FU) 459 #define GPR3_XPAR4_DIS_SHIFT (0U) 460 #define GPR3_XPAR4_DIS_WIDTH (6U) 461 #define GPR3_XPAR4_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPR3_XPAR4_DIS_SHIFT)) & GPR3_XPAR4_DIS_MASK) 462 463 #define GPR3_XPAR4_STAT_MASK (0x3F00U) 464 #define GPR3_XPAR4_STAT_SHIFT (8U) 465 #define GPR3_XPAR4_STAT_WIDTH (6U) 466 #define GPR3_XPAR4_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPR3_XPAR4_STAT_SHIFT)) & GPR3_XPAR4_STAT_MASK) 467 /*! @} */ 468 469 /*! @name RTU0XPAR - RTU0 global parity control register */ 470 /*! @{ */ 471 472 #define GPR3_RTU0XPAR_DIS_MASK (0x1U) 473 #define GPR3_RTU0XPAR_DIS_SHIFT (0U) 474 #define GPR3_RTU0XPAR_DIS_WIDTH (1U) 475 #define GPR3_RTU0XPAR_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPR3_RTU0XPAR_DIS_SHIFT)) & GPR3_RTU0XPAR_DIS_MASK) 476 /*! @} */ 477 478 /*! @name RTU1XPAR - RTU1 global parity control register */ 479 /*! @{ */ 480 481 #define GPR3_RTU1XPAR_DIS_MASK (0x1U) 482 #define GPR3_RTU1XPAR_DIS_SHIFT (0U) 483 #define GPR3_RTU1XPAR_DIS_WIDTH (1U) 484 #define GPR3_RTU1XPAR_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPR3_RTU1XPAR_DIS_SHIFT)) & GPR3_RTU1XPAR_DIS_MASK) 485 /*! @} */ 486 487 /*! 488 * @} 489 */ /* end of group GPR3_Register_Masks */ 490 491 /*! 492 * @} 493 */ /* end of group GPR3_Peripheral_Access_Layer */ 494 495 #endif /* #if !defined(S32Z2_GPR3_H_) */ 496
