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Searched refs:GPR2 (Results 1 – 25 of 69) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/drivers/
Dfsl_iomuxc.h522 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; in IOMUXC_MQSEnterSoftwareReset()
526 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; in IOMUXC_MQSEnterSoftwareReset()
540 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; in IOMUXC_MQSEnable()
544 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; in IOMUXC_MQSEnable()
558 …uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MA… in IOMUXC_MQSConfig()
559 base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); in IOMUXC_MQSConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/drivers/
Dfsl_iomuxc.h543 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; in IOMUXC_MQSEnterSoftwareReset()
547 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; in IOMUXC_MQSEnterSoftwareReset()
561 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; in IOMUXC_MQSEnable()
565 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; in IOMUXC_MQSEnable()
579 …uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MA… in IOMUXC_MQSConfig()
580 base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); in IOMUXC_MQSConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/drivers/
Dfsl_iomuxc.h960 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; in IOMUXC_MQSEnterSoftwareReset()
964 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; in IOMUXC_MQSEnterSoftwareReset()
978 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; in IOMUXC_MQSEnable()
982 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; in IOMUXC_MQSEnable()
996 …uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MA… in IOMUXC_MQSConfig()
997 base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); in IOMUXC_MQSConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/drivers/
Dfsl_iomuxc.h906 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; in IOMUXC_MQSEnterSoftwareReset()
910 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; in IOMUXC_MQSEnterSoftwareReset()
924 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; in IOMUXC_MQSEnable()
928 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; in IOMUXC_MQSEnable()
942 …uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MA… in IOMUXC_MQSConfig()
943 base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); in IOMUXC_MQSConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/drivers/
Dfsl_iomuxc.h1108 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; in IOMUXC_MQSEnterSoftwareReset()
1112 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; in IOMUXC_MQSEnterSoftwareReset()
1126 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; in IOMUXC_MQSEnable()
1130 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; in IOMUXC_MQSEnable()
1144 …uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MA… in IOMUXC_MQSConfig()
1145 base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); in IOMUXC_MQSConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/drivers/
Dfsl_iomuxc.h1108 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; in IOMUXC_MQSEnterSoftwareReset()
1112 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; in IOMUXC_MQSEnterSoftwareReset()
1126 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; in IOMUXC_MQSEnable()
1130 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; in IOMUXC_MQSEnable()
1144 …uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MA… in IOMUXC_MQSConfig()
1145 base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); in IOMUXC_MQSConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/drivers/
Dfsl_iomuxc.h1193 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; in IOMUXC_MQSEnterSoftwareReset()
1197 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; in IOMUXC_MQSEnterSoftwareReset()
1211 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; in IOMUXC_MQSEnable()
1215 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; in IOMUXC_MQSEnable()
1229 …uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MA… in IOMUXC_MQSConfig()
1230 base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); in IOMUXC_MQSConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/drivers/
Dfsl_iomuxc.h1193 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; in IOMUXC_MQSEnterSoftwareReset()
1197 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; in IOMUXC_MQSEnterSoftwareReset()
1211 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; in IOMUXC_MQSEnable()
1215 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; in IOMUXC_MQSEnable()
1229 …uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MA… in IOMUXC_MQSConfig()
1230 base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); in IOMUXC_MQSConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/drivers/
Dfsl_iomuxc.h1389 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; in IOMUXC_MQSEnterSoftwareReset()
1393 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; in IOMUXC_MQSEnterSoftwareReset()
1407 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; in IOMUXC_MQSEnable()
1411 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; in IOMUXC_MQSEnable()
1425 …uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MA… in IOMUXC_MQSConfig()
1426 base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); in IOMUXC_MQSConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/drivers/
Dfsl_iomuxc.h1389 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; in IOMUXC_MQSEnterSoftwareReset()
1393 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; in IOMUXC_MQSEnterSoftwareReset()
1407 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; in IOMUXC_MQSEnable()
1411 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; in IOMUXC_MQSEnable()
1425 …uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MA… in IOMUXC_MQSConfig()
1426 base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); in IOMUXC_MQSConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/drivers/
Dfsl_iomuxc.h1373 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; in IOMUXC_MQSEnterSoftwareReset()
1377 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; in IOMUXC_MQSEnterSoftwareReset()
1391 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; in IOMUXC_MQSEnable()
1395 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; in IOMUXC_MQSEnable()
1409 …uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MA… in IOMUXC_MQSConfig()
1410 base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); in IOMUXC_MQSConfig()
/hal_nxp-latest/mcux/mcux-sdk/drivers/iee_apc/
Dfsl_iee_apc.c99 IOMUXC_LPSR_GPR->GPR2 |= startAddr & IOMUXC_LPSR_GPR_APC_ADDR_MASK; in IEE_APC_SetRegionConfig()
319 IOMUXC_LPSR_GPR->GPR2 |= IOMUXC_LPSR_GPR_GPR2_LOCK(1); in IEE_APC_LockRegionConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_iomuxc.h1691 gpr = base->GPR2 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK); in IOMUXC_SetSaiMClkClockSource()
1692 base->GPR2 = ((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_iomuxc.h1691 gpr = base->GPR2 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK); in IOMUXC_SetSaiMClkClockSource()
1692 base->GPR2 = ((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_iomuxc.h1691 gpr = base->GPR2 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK); in IOMUXC_SetSaiMClkClockSource()
1692 base->GPR2 = ((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_iomuxc.h1691 gpr = base->GPR2 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK); in IOMUXC_SetSaiMClkClockSource()
1692 base->GPR2 = ((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_iomuxc.h1691 gpr = base->GPR2 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK); in IOMUXC_SetSaiMClkClockSource()
1692 base->GPR2 = ((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_iomuxc.h1691 gpr = base->GPR2 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK); in IOMUXC_SetSaiMClkClockSource()
1692 base->GPR2 = ((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_iomuxc.h1691 gpr = base->GPR2 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK); in IOMUXC_SetSaiMClkClockSource()
1692 base->GPR2 = ((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h23247 …__IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset:… member
23273 #define IOMUXC_GPR_GPR2_REG(base) ((base)->GPR2)
34162 …__IO uint32_t GPR2; /**< SRC General Purpose Register 2, offset… member
34190 #define SRC_GPR2_REG(base) ((base)->GPR2)
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h26557 …__IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset:… member
26592 #define IOMUXC_GPR_GPR2_REG(base) ((base)->GPR2)
40538 …__IO uint32_t GPR2; /**< SRC General Purpose Register 2, offset… member
40577 #define SRC_GPR2_REG(base) ((base)->GPR2)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h16410 …__IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ member
17859 … uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h18912 …__IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ member
20808 … uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h22232 …__IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ member
24819 … uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h22253 …__IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ member
24840 … uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ member

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