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Searched refs:GPR1 (Results 1 – 25 of 92) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/drivers/
Dfsl_iomuxc.h481 base->GPR1 |= mode; in IOMUXC_EnableMode()
485 base->GPR1 &= ~mode; in IOMUXC_EnableMode()
502 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
503 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
507 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
508 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/drivers/
Dfsl_iomuxc.h502 base->GPR1 |= mode; in IOMUXC_EnableMode()
506 base->GPR1 &= ~mode; in IOMUXC_EnableMode()
523 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
524 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
528 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
529 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/drivers/
Dfsl_iomuxc.h865 base->GPR1 |= mode; in IOMUXC_EnableMode()
869 base->GPR1 &= ~mode; in IOMUXC_EnableMode()
886 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
887 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
891 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
892 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/drivers/
Dfsl_iomuxc.h919 base->GPR1 |= mode; in IOMUXC_EnableMode()
923 base->GPR1 &= ~mode; in IOMUXC_EnableMode()
940 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
941 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
945 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
946 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/drivers/
Dfsl_iomuxc.h1067 base->GPR1 |= mode; in IOMUXC_EnableMode()
1071 base->GPR1 &= ~mode; in IOMUXC_EnableMode()
1088 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1089 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
1093 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1094 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/drivers/
Dfsl_iomuxc.h1067 base->GPR1 |= mode; in IOMUXC_EnableMode()
1071 base->GPR1 &= ~mode; in IOMUXC_EnableMode()
1088 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1089 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
1093 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1094 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/drivers/
Dfsl_iomuxc.h1152 base->GPR1 |= mode; in IOMUXC_EnableMode()
1156 base->GPR1 &= ~mode; in IOMUXC_EnableMode()
1173 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1174 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
1178 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1179 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/drivers/
Dfsl_iomuxc.h1152 base->GPR1 |= mode; in IOMUXC_EnableMode()
1156 base->GPR1 &= ~mode; in IOMUXC_EnableMode()
1173 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1174 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
1178 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1179 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/drivers/
Dfsl_iomuxc.h1348 base->GPR1 |= mode; in IOMUXC_EnableMode()
1352 base->GPR1 &= ~mode; in IOMUXC_EnableMode()
1369 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1370 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
1374 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1375 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/drivers/
Dfsl_iomuxc.h1332 base->GPR1 |= mode; in IOMUXC_EnableMode()
1336 base->GPR1 &= ~mode; in IOMUXC_EnableMode()
1353 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1354 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
1358 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1359 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/drivers/
Dfsl_iomuxc.h1348 base->GPR1 |= mode; in IOMUXC_EnableMode()
1352 base->GPR1 &= ~mode; in IOMUXC_EnableMode()
1369 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1370 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
1374 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1375 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1020/
Dclock_config.c414 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; in BOARD_BootClockRUN()
417 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
783 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; in BOARD_BootClockRUN_400M()
786 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN_400M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1024/
Dclock_config.c414 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; in BOARD_BootClockRUN()
417 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
783 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; in BOARD_BootClockRUN_400M()
786 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN_400M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkbimxrt1050/
Dclock_config.c482 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; in BOARD_BootClockRUN()
485 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
921 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; in BOARD_BootClockRUN_528M()
924 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN_528M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1060/
Dclock_config.c500 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
502 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
953 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN_528M()
955 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; in BOARD_BootClockRUN_528M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkbmimxrt1060/
Dclock_config.c500 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
502 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
953 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN_528M()
955 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; in BOARD_BootClockRUN_528M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1064/
Dclock_config.c502 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
504 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
957 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN_528M()
959 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; in BOARD_BootClockRUN_528M()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkcmimxrt1060/
Dclock_config.c499 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
501 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
952 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN_528M()
954 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; in BOARD_BootClockRUN_528M()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/mcuxpresso/
Dboot_multicore_slave.c50 IOMUXC_LPSR_GPR->GPR1 = IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH(bootAddress >> 16u); in boot_multicore_slave()
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimxrt1040/
Dclock_config.c471 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN()
905 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; in BOARD_BootClockRUN_600M()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_iomuxc.h1696 gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK); in IOMUXC_SetSaiMClkClockSource()
1697 base->GPR1 = ((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_iomuxc.h1696 gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK); in IOMUXC_SetSaiMClkClockSource()
1697 base->GPR1 = ((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_iomuxc.h1696 gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK); in IOMUXC_SetSaiMClkClockSource()
1697 base->GPR1 = ((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_iomuxc.h1696 gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK); in IOMUXC_SetSaiMClkClockSource()
1697 base->GPR1 = ((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_iomuxc.h1696 gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK); in IOMUXC_SetSaiMClkClockSource()
1697 base->GPR1 = ((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) | gpr; in IOMUXC_SetSaiMClkClockSource()

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