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Searched refs:GPIO_ICR1_ICR0_MASK (Results 1 – 25 of 69) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h14594 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
14602 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h17088 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
17096 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h20407 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
20415 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h20427 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
20435 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h21364 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
21372 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h22551 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
22559 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h22149 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
22157 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h22553 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
22561 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h22929 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
22937 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h31280 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
31288 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h31278 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
31286 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h31278 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
31286 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h31280 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
31288 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h23786 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
23794 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h31280 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
31288 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_cm7.h31278 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
31286 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
DMIMX8MN6_ca53.h31306 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
31314 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h28834 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
28842 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h23715 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
23723 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h28834 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
28842 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h28834 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
28842 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h13783 #define GPIO_ICR1_ICR0_MASK 0x3u macro
13785 …x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR0_SHIFT))&GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h28834 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
28842 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h28834 #define GPIO_ICR1_ICR0_MASK (0x3U) macro
28842 … (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h19775 #define GPIO_ICR1_ICR0_MASK 0x3u macro
19777 …x) (((uint32_t)(((uint32_t)(x))<<GPIO_ICR1_ICR0_SHIFT))&GPIO_ICR1_ICR0_MASK)

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