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Searched refs:GPC_CPU_MODE_CTRL_1_BASE (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h39016 #define GPC_CPU_MODE_CTRL_1_BASE (0x40C00800u) macro
39018 …efine GPC_CPU_MODE_CTRL_1 ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE)
39020 …ine GPC_CPU_MODE_CTRL_BASE_ADDRS { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE }
DMIMXRT1175_cm7.h39019 #define GPC_CPU_MODE_CTRL_1_BASE (0x40C00800u) macro
39021 …efine GPC_CPU_MODE_CTRL_1 ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE)
39023 …ine GPC_CPU_MODE_CTRL_BASE_ADDRS { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h38543 #define GPC_CPU_MODE_CTRL_1_BASE (0x40C00800u) macro
38545 …efine GPC_CPU_MODE_CTRL_1 ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE)
38547 …ine GPC_CPU_MODE_CTRL_BASE_ADDRS { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE }
DMIMXRT1165_cm4.h38540 #define GPC_CPU_MODE_CTRL_1_BASE (0x40C00800u) macro
38542 …efine GPC_CPU_MODE_CTRL_1 ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE)
38544 …ine GPC_CPU_MODE_CTRL_BASE_ADDRS { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h39019 #define GPC_CPU_MODE_CTRL_1_BASE (0x40C00800u) macro
39021 …efine GPC_CPU_MODE_CTRL_1 ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE)
39023 …ine GPC_CPU_MODE_CTRL_BASE_ADDRS { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h40545 #define GPC_CPU_MODE_CTRL_1_BASE (0x40C00800u) macro
40547 …efine GPC_CPU_MODE_CTRL_1 ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE)
40549 …ine GPC_CPU_MODE_CTRL_BASE_ADDRS { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE }
DMIMXRT1166_cm7.h40548 #define GPC_CPU_MODE_CTRL_1_BASE (0x40C00800u) macro
40550 …efine GPC_CPU_MODE_CTRL_1 ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE)
40552 …ine GPC_CPU_MODE_CTRL_BASE_ADDRS { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h41018 #define GPC_CPU_MODE_CTRL_1_BASE (0x40C00800u) macro
41020 …efine GPC_CPU_MODE_CTRL_1 ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE)
41022 …ine GPC_CPU_MODE_CTRL_BASE_ADDRS { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE }
DMIMXRT1173_cm7.h41021 #define GPC_CPU_MODE_CTRL_1_BASE (0x40C00800u) macro
41023 …efine GPC_CPU_MODE_CTRL_1 ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE)
41025 …ine GPC_CPU_MODE_CTRL_BASE_ADDRS { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h41024 #define GPC_CPU_MODE_CTRL_1_BASE (0x40C00800u) macro
41026 …efine GPC_CPU_MODE_CTRL_1 ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE)
41028 …ine GPC_CPU_MODE_CTRL_BASE_ADDRS { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h51691 #define GPC_CPU_MODE_CTRL_1_BASE (0x40C00800u) macro
51693 …efine GPC_CPU_MODE_CTRL_1 ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE)
51695 …ine GPC_CPU_MODE_CTRL_BASE_ADDRS { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE }
DMIMXRT1176_cm4.h51688 #define GPC_CPU_MODE_CTRL_1_BASE (0x40C00800u) macro
51690 …efine GPC_CPU_MODE_CTRL_1 ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE)
51692 …ine GPC_CPU_MODE_CTRL_BASE_ADDRS { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE }