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Searched refs:GENFSK_IRQ_CTRL_CRC_VALID_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MKW31Z4/
DMKW31Z4.h2710 #define GENFSK_IRQ_CTRL_CRC_VALID_MASK (0x80000000U) macro
2712 …(((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_CRC_VALID_SHIFT)) & GENFSK_IRQ_CTRL_CRC_VALID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW21Z4/
DMKW21Z4.h2639 #define GENFSK_IRQ_CTRL_CRC_VALID_MASK (0x80000000U) macro
2641 …(((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_CRC_VALID_SHIFT)) & GENFSK_IRQ_CTRL_CRC_VALID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW41Z4/
DMKW41Z4.h2710 #define GENFSK_IRQ_CTRL_CRC_VALID_MASK (0x80000000U) macro
2712 …(((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_CRC_VALID_SHIFT)) & GENFSK_IRQ_CTRL_CRC_VALID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/
DMCXW716A.h10864 #define GENFSK_IRQ_CTRL_CRC_VALID_MASK (0x400U) macro
10867 …(((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_CRC_VALID_SHIFT)) & GENFSK_IRQ_CTRL_CRC_VALID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/
DMCXW716C.h13033 #define GENFSK_IRQ_CTRL_CRC_VALID_MASK (0x400U) macro
13036 …(((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_CRC_VALID_SHIFT)) & GENFSK_IRQ_CTRL_CRC_VALID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/
DMCXW727C_cm33_core0.h13573 #define GENFSK_IRQ_CTRL_CRC_VALID_MASK (0x400U) macro
13576 …(((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_CRC_VALID_SHIFT)) & GENFSK_IRQ_CTRL_CRC_VALID_MASK)
DMCXW727C_cm33_core1.h21921 #define GENFSK_IRQ_CTRL_CRC_VALID_MASK (0x400U) macro
21924 …(((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_CRC_VALID_SHIFT)) & GENFSK_IRQ_CTRL_CRC_VALID_MASK)