Searched refs:GEN4PHY_DMD_WAVE_REG0_SMPL3_MASK (Results 1 – 4 of 4) sorted by relevance
10441 #define GEN4PHY_DMD_WAVE_REG0_SMPL3_MASK (0xFC0000U) macro10444 …int32_t)(((uint32_t)(x)) << GEN4PHY_DMD_WAVE_REG0_SMPL3_SHIFT)) & GEN4PHY_DMD_WAVE_REG0_SMPL3_MASK)
12610 #define GEN4PHY_DMD_WAVE_REG0_SMPL3_MASK (0xFC0000U) macro12613 …int32_t)(((uint32_t)(x)) << GEN4PHY_DMD_WAVE_REG0_SMPL3_SHIFT)) & GEN4PHY_DMD_WAVE_REG0_SMPL3_MASK)
13150 #define GEN4PHY_DMD_WAVE_REG0_SMPL3_MASK (0xFC0000U) macro13153 …int32_t)(((uint32_t)(x)) << GEN4PHY_DMD_WAVE_REG0_SMPL3_SHIFT)) & GEN4PHY_DMD_WAVE_REG0_SMPL3_MASK)
21498 #define GEN4PHY_DMD_WAVE_REG0_SMPL3_MASK (0xFC0000U) macro21501 …int32_t)(((uint32_t)(x)) << GEN4PHY_DMD_WAVE_REG0_SMPL3_SHIFT)) & GEN4PHY_DMD_WAVE_REG0_SMPL3_MASK)
