Searched refs:GEN4PHY_DMD_WAVE_REG0_SMPL1_MASK (Results 1 – 4 of 4) sorted by relevance
10431 #define GEN4PHY_DMD_WAVE_REG0_SMPL1_MASK (0xFC0U) macro10434 …int32_t)(((uint32_t)(x)) << GEN4PHY_DMD_WAVE_REG0_SMPL1_SHIFT)) & GEN4PHY_DMD_WAVE_REG0_SMPL1_MASK)
12600 #define GEN4PHY_DMD_WAVE_REG0_SMPL1_MASK (0xFC0U) macro12603 …int32_t)(((uint32_t)(x)) << GEN4PHY_DMD_WAVE_REG0_SMPL1_SHIFT)) & GEN4PHY_DMD_WAVE_REG0_SMPL1_MASK)
13140 #define GEN4PHY_DMD_WAVE_REG0_SMPL1_MASK (0xFC0U) macro13143 …int32_t)(((uint32_t)(x)) << GEN4PHY_DMD_WAVE_REG0_SMPL1_SHIFT)) & GEN4PHY_DMD_WAVE_REG0_SMPL1_MASK)
21488 #define GEN4PHY_DMD_WAVE_REG0_SMPL1_MASK (0xFC0U) macro21491 …int32_t)(((uint32_t)(x)) << GEN4PHY_DMD_WAVE_REG0_SMPL1_SHIFT)) & GEN4PHY_DMD_WAVE_REG0_SMPL1_MASK)
