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Searched refs:FRGPLLCLKDIV (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_clock.c577 frgPllDiv = (CLKCTL1->FRGPLLCLKDIV & CLKCTL1_FRGPLLCLKDIV_DIV_MASK) + 1U; in CLOCK_GetFRGClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_clock.c577 frgPllDiv = (CLKCTL1->FRGPLLCLKDIV & CLKCTL1_FRGPLLCLKDIV_DIV_MASK) + 1U; in CLOCK_GetFRGClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/drivers/
Dfsl_clock.c667 frgPllDiv = (CLKCTL1->FRGPLLCLKDIV & CLKCTL1_FRGPLLCLKDIV_DIV_MASK) + 1U; in CLOCK_GetFRGClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/drivers/
Dfsl_clock.c667 frgPllDiv = (CLKCTL1->FRGPLLCLKDIV & CLKCTL1_FRGPLLCLKDIV_DIV_MASK) + 1U; in CLOCK_GetFRGClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_clock.c569 frgPllDiv = (CLKCTL1->FRGPLLCLKDIV & CLKCTL1_FRGPLLCLKDIV_DIV_MASK) + 1U; in CLOCK_GetFRGClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_clock.c569 frgPllDiv = (CLKCTL1->FRGPLLCLKDIV & CLKCTL1_FRGPLLCLKDIV_DIV_MASK) + 1U; in CLOCK_GetFRGClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_clock.c569 frgPllDiv = (CLKCTL1->FRGPLLCLKDIV & CLKCTL1_FRGPLLCLKDIV_DIV_MASK) + 1U; in CLOCK_GetFRGClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h2759 __IO uint32_t FRGPLLCLKDIV; /**< FRG pll clock divider, offset: 0x6FC */ member
DMIMXRT685S_cm33.h8489 __IO uint32_t FRGPLLCLKDIV; /**< FRG pll clock divider, offset: 0x6FC */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h8489 __IO uint32_t FRGPLLCLKDIV; /**< FRG pll clock divider, offset: 0x6FC */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h4145 …__IO uint32_t FRGPLLCLKDIV; /**< Fractional Rate Generator PLL Clock Divider,… member
DMIMXRT595S_cm33.h10402 …__IO uint32_t FRGPLLCLKDIV; /**< Fractional Rate Generator PLL Clock Divider,… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h10398 …__IO uint32_t FRGPLLCLKDIV; /**< Fractional Rate Generator PLL Clock Divider,… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h10401 …__IO uint32_t FRGPLLCLKDIV; /**< Fractional Rate Generator PLL Clock Divider,… member
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h21438 __IO uint32_t FRGPLLCLKDIV; /**< FRG PLL clock divider, offset: 0x6FC */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h21438 __IO uint32_t FRGPLLCLKDIV; /**< FRG PLL clock divider, offset: 0x6FC */ member