Searched refs:FRG15CTL (Results 1 – 5 of 5) sorted by relevance
562 frgMul = ((CLKCTL1->FRG15CTL) & CLKCTL1_FRGCTL_MULT_MASK) >> CLKCTL1_FRGCTL_MULT_SHIFT; in CLOCK_GetFRGClock()563 frgDiv = ((CLKCTL1->FRG15CTL) & CLKCTL1_FRGCTL_DIV_MASK) >> CLKCTL1_FRGCTL_DIV_SHIFT; in CLOCK_GetFRGClock()1166 … CLKCTL1->FRG15CTL = (CLKCTL1_FRGCTL_MULT(config->mult) | CLKCTL1_FRGCTL_DIV(config->divider)); in CLOCK_SetFRGClock()
2756 __IO uint32_t FRG15CTL; /**< FRG clock controller 15, offset: 0x6E4 */ member
8486 __IO uint32_t FRG15CTL; /**< FRG clock controller 15, offset: 0x6E4 */ member