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Searched refs:FLEXSPI_INTR_AHBCMDGE_MASK (Results 1 – 25 of 94) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/flexspi/
Dfsl_flexspi.c848 …ase->INTR = FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | in FLEXSPI_TransferBlocking()
972 …ase->INTR = FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | in FLEXSPI_TransferNonBlocking()
Dfsl_flexspi_edma.c186 …se->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | in FLEXSPI_TransferEDMA()
Dfsl_flexspi_dma.c537 …se->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | in FLEXSPI_TransferDMA()
/hal_nxp-latest/mcux/mcux-sdk/drivers/flexspi/flexspi_dma3/
Dfsl_flexspi_edma.c202 …se->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | in FLEXSPI_TransferEDMA()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h7448 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) macro
7451 … (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
DMIMXRT685S_cm33.h13425 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) macro
13428 … (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h13742 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) macro
13745 … (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h16246 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) macro
16249 … (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h13425 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) macro
13428 … (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h13379 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) macro
13382 … (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
DMIMXRT595S_cm33.h19977 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) macro
19980 … (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h19565 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) macro
19568 … (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h13868 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) macro
13876 … (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h13868 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) macro
13876 … (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h19585 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) macro
19588 … (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h20530 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) macro
20533 … (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h21695 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) macro
21698 … (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h21315 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) macro
21318 … (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h21697 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) macro
21700 … (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h19973 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) macro
19976 … (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h22072 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) macro
22075 … (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h19976 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) macro
19979 … (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h22930 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) macro
22933 … (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h13867 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) macro
13875 … (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h22858 #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) macro
22861 … (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)

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