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Searched refs:FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h13142 #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) macro
13145 …int32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h35706 #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFC0000U) macro
35709 …int32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)
DMIMXRT1175_cm7.h35708 #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFC0000U) macro
35711 …int32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h35396 #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFC0000U) macro
35399 …int32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)
DMIMXRT1165_cm4.h35394 #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFC0000U) macro
35397 …int32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h35708 #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFC0000U) macro
35711 …int32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h37399 #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFC0000U) macro
37402 …int32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)
DMIMXRT1166_cm7.h37401 #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFC0000U) macro
37404 …int32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h37708 #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFC0000U) macro
37711 …int32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)
DMIMXRT1173_cm7.h37710 #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFC0000U) macro
37713 …int32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h37713 #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFC0000U) macro
37716 …int32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h48380 #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFC0000U) macro
48383 …int32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)
DMIMXRT1176_cm4.h48378 #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFC0000U) macro
48381 …int32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)