1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_FEED_DMACRC.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_FEED_DMACRC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_FEED_DMACRC_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_FEED_DMACRC_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- FEED_DMACRC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup FEED_DMACRC_Peripheral_Access_Layer FEED_DMACRC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** FEED_DMACRC - Size of Registers Arrays */ 72 #define FEED_DMACRC_CONTROL_REGISTER_COUNT 8u 73 74 /** FEED_DMACRC - Register Layout Typedef */ 75 typedef struct { 76 __IO uint32_t GEC; /**< Global Enable CRC Register, offset: 0x0 */ 77 uint8_t RESERVED_0[12]; 78 struct FEED_DMACRC_CONTROL_REGISTER { /* offset: 0x10, array step: 0x10 */ 79 __IO uint32_t CTL; /**< CRC Control Register, array offset: 0x10, array step: 0x10 */ 80 __IO uint32_t ICRC; /**< Initial CRC Value Register, array offset: 0x14, array step: 0x10 */ 81 __I uint32_t FCRC; /**< Final CRC Value Register, array offset: 0x18, array step: 0x10 */ 82 uint8_t RESERVED_0[4]; 83 } CONTROL_REGISTER[FEED_DMACRC_CONTROL_REGISTER_COUNT]; 84 } FEED_DMACRC_Type, *FEED_DMACRC_MemMapPtr; 85 86 /** Number of instances of the FEED_DMACRC module. */ 87 #define FEED_DMACRC_INSTANCE_COUNT (1u) 88 89 /* FEED_DMACRC - Peripheral instance base addresses */ 90 /** Peripheral AES__FEED_DMACRC base address */ 91 #define IP_AES__FEED_DMACRC_BASE (0x47230000u) 92 /** Peripheral AES__FEED_DMACRC base pointer */ 93 #define IP_AES__FEED_DMACRC ((FEED_DMACRC_Type *)IP_AES__FEED_DMACRC_BASE) 94 /** Array initializer of FEED_DMACRC peripheral base addresses */ 95 #define IP_FEED_DMACRC_BASE_ADDRS { IP_AES__FEED_DMACRC_BASE } 96 /** Array initializer of FEED_DMACRC peripheral base pointers */ 97 #define IP_FEED_DMACRC_BASE_PTRS { IP_AES__FEED_DMACRC } 98 99 /* ---------------------------------------------------------------------------- 100 -- FEED_DMACRC Register Masks 101 ---------------------------------------------------------------------------- */ 102 103 /*! 104 * @addtogroup FEED_DMACRC_Register_Masks FEED_DMACRC Register Masks 105 * @{ 106 */ 107 108 /*! @name GEC - Global Enable CRC Register */ 109 /*! @{ */ 110 111 #define FEED_DMACRC_GEC_GBL_EN_MASK (0x1U) 112 #define FEED_DMACRC_GEC_GBL_EN_SHIFT (0U) 113 #define FEED_DMACRC_GEC_GBL_EN_WIDTH (1U) 114 #define FEED_DMACRC_GEC_GBL_EN(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMACRC_GEC_GBL_EN_SHIFT)) & FEED_DMACRC_GEC_GBL_EN_MASK) 115 116 #define FEED_DMACRC_GEC_SWAP_BYTE_MASK (0x80U) 117 #define FEED_DMACRC_GEC_SWAP_BYTE_SHIFT (7U) 118 #define FEED_DMACRC_GEC_SWAP_BYTE_WIDTH (1U) 119 #define FEED_DMACRC_GEC_SWAP_BYTE(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMACRC_GEC_SWAP_BYTE_SHIFT)) & FEED_DMACRC_GEC_SWAP_BYTE_MASK) 120 /*! @} */ 121 122 /*! @name CTL - CRC Control Register */ 123 /*! @{ */ 124 125 #define FEED_DMACRC_CTL_CH_SEL_MASK (0x1FU) 126 #define FEED_DMACRC_CTL_CH_SEL_SHIFT (0U) 127 #define FEED_DMACRC_CTL_CH_SEL_WIDTH (5U) 128 #define FEED_DMACRC_CTL_CH_SEL(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMACRC_CTL_CH_SEL_SHIFT)) & FEED_DMACRC_CTL_CH_SEL_MASK) 129 130 #define FEED_DMACRC_CTL_POLY_SEL_MASK (0x700U) 131 #define FEED_DMACRC_CTL_POLY_SEL_SHIFT (8U) 132 #define FEED_DMACRC_CTL_POLY_SEL_WIDTH (3U) 133 #define FEED_DMACRC_CTL_POLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMACRC_CTL_POLY_SEL_SHIFT)) & FEED_DMACRC_CTL_POLY_SEL_MASK) 134 135 #define FEED_DMACRC_CTL_CS_XOR_MASK (0x1000U) 136 #define FEED_DMACRC_CTL_CS_XOR_SHIFT (12U) 137 #define FEED_DMACRC_CTL_CS_XOR_WIDTH (1U) 138 #define FEED_DMACRC_CTL_CS_XOR(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMACRC_CTL_CS_XOR_SHIFT)) & FEED_DMACRC_CTL_CS_XOR_MASK) 139 140 #define FEED_DMACRC_CTL_CS_SWAP_MASK (0x2000U) 141 #define FEED_DMACRC_CTL_CS_SWAP_SHIFT (13U) 142 #define FEED_DMACRC_CTL_CS_SWAP_WIDTH (1U) 143 #define FEED_DMACRC_CTL_CS_SWAP(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMACRC_CTL_CS_SWAP_SHIFT)) & FEED_DMACRC_CTL_CS_SWAP_MASK) 144 145 #define FEED_DMACRC_CTL_SWAP_BIT_MASK (0x4000U) 146 #define FEED_DMACRC_CTL_SWAP_BIT_SHIFT (14U) 147 #define FEED_DMACRC_CTL_SWAP_BIT_WIDTH (1U) 148 #define FEED_DMACRC_CTL_SWAP_BIT(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMACRC_CTL_SWAP_BIT_SHIFT)) & FEED_DMACRC_CTL_SWAP_BIT_MASK) 149 150 #define FEED_DMACRC_CTL_INIT_SEL_MASK (0x8000U) 151 #define FEED_DMACRC_CTL_INIT_SEL_SHIFT (15U) 152 #define FEED_DMACRC_CTL_INIT_SEL_WIDTH (1U) 153 #define FEED_DMACRC_CTL_INIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMACRC_CTL_INIT_SEL_SHIFT)) & FEED_DMACRC_CTL_INIT_SEL_MASK) 154 155 #define FEED_DMACRC_CTL_MODE_MASK (0x70000U) 156 #define FEED_DMACRC_CTL_MODE_SHIFT (16U) 157 #define FEED_DMACRC_CTL_MODE_WIDTH (3U) 158 #define FEED_DMACRC_CTL_MODE(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMACRC_CTL_MODE_SHIFT)) & FEED_DMACRC_CTL_MODE_MASK) 159 160 #define FEED_DMACRC_CTL_EN_MASK (0x80000000U) 161 #define FEED_DMACRC_CTL_EN_SHIFT (31U) 162 #define FEED_DMACRC_CTL_EN_WIDTH (1U) 163 #define FEED_DMACRC_CTL_EN(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMACRC_CTL_EN_SHIFT)) & FEED_DMACRC_CTL_EN_MASK) 164 /*! @} */ 165 166 /*! @name ICRC - Initial CRC Value Register */ 167 /*! @{ */ 168 169 #define FEED_DMACRC_ICRC_INI_CRC_VAL_MASK (0xFFFFFFFFU) 170 #define FEED_DMACRC_ICRC_INI_CRC_VAL_SHIFT (0U) 171 #define FEED_DMACRC_ICRC_INI_CRC_VAL_WIDTH (32U) 172 #define FEED_DMACRC_ICRC_INI_CRC_VAL(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMACRC_ICRC_INI_CRC_VAL_SHIFT)) & FEED_DMACRC_ICRC_INI_CRC_VAL_MASK) 173 /*! @} */ 174 175 /*! @name FCRC - Final CRC Value Register */ 176 /*! @{ */ 177 178 #define FEED_DMACRC_FCRC_CHKSUM_VAL_MASK (0xFFFFFFFFU) 179 #define FEED_DMACRC_FCRC_CHKSUM_VAL_SHIFT (0U) 180 #define FEED_DMACRC_FCRC_CHKSUM_VAL_WIDTH (32U) 181 #define FEED_DMACRC_FCRC_CHKSUM_VAL(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMACRC_FCRC_CHKSUM_VAL_SHIFT)) & FEED_DMACRC_FCRC_CHKSUM_VAL_MASK) 182 /*! @} */ 183 184 /*! 185 * @} 186 */ /* end of group FEED_DMACRC_Register_Masks */ 187 188 /*! 189 * @} 190 */ /* end of group FEED_DMACRC_Peripheral_Access_Layer */ 191 192 #endif /* #if !defined(S32Z2_FEED_DMACRC_H_) */ 193
