Searched refs:ExpectedFifoWrites (Results 1 – 2 of 2) sorted by relevance
342 if (State->CurrentTxFifoSlot > (State->ExpectedFifoWrites - State->TxIndex)) in Spi_Ip_TransferProcess()344 State->CurrentTxFifoSlot = State->ExpectedFifoWrites - State->TxIndex; in Spi_Ip_TransferProcess()577 State->ExpectedFifoWrites = NbBytes / TxBytesPerWord; in Spi_Ip_PrepareTransfer()673 State->TxIndex = State->ExpectedFifoWrites; in Spi_Ip_TxDmaTcdSGConfig()700 DmaTcdList[5u].Value = State->ExpectedFifoWrites; /* iteration count */ in Spi_Ip_TxDmaTcdSGConfig()1014 uint16 NumberDmaIterWrite = State->ExpectedFifoWrites - State->TxIndex; in Spi_Ip_DmaTxRxUpdateLoop()1282 uint16 RemainingWrites = State->ExpectedFifoWrites - State->TxIndex; in Spi_Ip_AsyncStart()1612 if (State->CurrentTxFifoSlot > (State->ExpectedFifoWrites - State->TxIndex)) in Spi_Ip_SyncReadWriteStep()1614 State->CurrentTxFifoSlot = State->ExpectedFifoWrites - State->TxIndex; in Spi_Ip_SyncReadWriteStep()1896 State->ExpectedFifoWrites = FastTransferCfg[Count].Length; in Spi_Ip_DmaFastConfig()[all …]
232 …uint16 ExpectedFifoWrites; /**< Store number of frames needs to be transmit for current transfer… member
