1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_ERROR_CORRECTION_CODES.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_ERROR_CORRECTION_CODES 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_ERROR_CORRECTION_CODES_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_ERROR_CORRECTION_CODES_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- ERROR_CORRECTION_CODES Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup ERROR_CORRECTION_CODES_Peripheral_Access_Layer ERROR_CORRECTION_CODES Peripheral Access Layer 68 * @{ 69 */ 70 71 /** ERROR_CORRECTION_CODES - Register Layout Typedef */ 72 typedef struct { 73 uint8_t RESERVED_0[4]; 74 __I uint32_t D_ECCCOR; /**< ECC Correctable Error Address, offset: 0x4 */ 75 __I uint32_t D_ECCERR; /**< ECC Uncorrectable Error Address, offset: 0x8 */ 76 } ERROR_CORRECTION_CODES_Type, *ERROR_CORRECTION_CODES_MemMapPtr; 77 78 /** Number of instances of the ERROR_CORRECTION_CODES module. */ 79 #define ERROR_CORRECTION_CODES_INSTANCE_COUNT (1u) 80 81 /* ERROR_CORRECTION_CODES - Peripheral instance base addresses */ 82 /** Peripheral CEVA_SPF2__ERROR_CORRECTION_CODES base address */ 83 #define IP_CEVA_SPF2__ERROR_CORRECTION_CODES_BASE (0x24400780u) 84 /** Peripheral CEVA_SPF2__ERROR_CORRECTION_CODES base pointer */ 85 #define IP_CEVA_SPF2__ERROR_CORRECTION_CODES ((ERROR_CORRECTION_CODES_Type *)IP_CEVA_SPF2__ERROR_CORRECTION_CODES_BASE) 86 /** Array initializer of ERROR_CORRECTION_CODES peripheral base addresses */ 87 #define IP_ERROR_CORRECTION_CODES_BASE_ADDRS { IP_CEVA_SPF2__ERROR_CORRECTION_CODES_BASE } 88 /** Array initializer of ERROR_CORRECTION_CODES peripheral base pointers */ 89 #define IP_ERROR_CORRECTION_CODES_BASE_PTRS { IP_CEVA_SPF2__ERROR_CORRECTION_CODES } 90 91 /* ---------------------------------------------------------------------------- 92 -- ERROR_CORRECTION_CODES Register Masks 93 ---------------------------------------------------------------------------- */ 94 95 /*! 96 * @addtogroup ERROR_CORRECTION_CODES_Register_Masks ERROR_CORRECTION_CODES Register Masks 97 * @{ 98 */ 99 100 /*! @name D_ECCCOR - ECC Correctable Error Address */ 101 /*! @{ */ 102 103 #define ERROR_CORRECTION_CODES_D_ECCCOR_D_ECCCORADD_MASK (0xFFFFFFFCU) 104 #define ERROR_CORRECTION_CODES_D_ECCCOR_D_ECCCORADD_SHIFT (2U) 105 #define ERROR_CORRECTION_CODES_D_ECCCOR_D_ECCCORADD_WIDTH (30U) 106 #define ERROR_CORRECTION_CODES_D_ECCCOR_D_ECCCORADD(x) (((uint32_t)(((uint32_t)(x)) << ERROR_CORRECTION_CODES_D_ECCCOR_D_ECCCORADD_SHIFT)) & ERROR_CORRECTION_CODES_D_ECCCOR_D_ECCCORADD_MASK) 107 /*! @} */ 108 109 /*! @name D_ECCERR - ECC Uncorrectable Error Address */ 110 /*! @{ */ 111 112 #define ERROR_CORRECTION_CODES_D_ECCERR_D_ECCERRADD_MASK (0xFFFFFFFCU) 113 #define ERROR_CORRECTION_CODES_D_ECCERR_D_ECCERRADD_SHIFT (2U) 114 #define ERROR_CORRECTION_CODES_D_ECCERR_D_ECCERRADD_WIDTH (30U) 115 #define ERROR_CORRECTION_CODES_D_ECCERR_D_ECCERRADD(x) (((uint32_t)(((uint32_t)(x)) << ERROR_CORRECTION_CODES_D_ECCERR_D_ECCERRADD_SHIFT)) & ERROR_CORRECTION_CODES_D_ECCERR_D_ECCERRADD_MASK) 116 /*! @} */ 117 118 /*! 119 * @} 120 */ /* end of group ERROR_CORRECTION_CODES_Register_Masks */ 121 122 /*! 123 * @} 124 */ /* end of group ERROR_CORRECTION_CODES_Peripheral_Access_Layer */ 125 126 #endif /* #if !defined(S32Z2_ERROR_CORRECTION_CODES_H_) */ 127
