Home
last modified time | relevance | path

Searched refs:ENET_MAC_MDIO_ADDRESS_CR_MASK (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/drivers/mcx_enet/
Dfsl_enet.c1018 uint32_t reg = base->MAC_MDIO_ADDRESS & ENET_MAC_MDIO_ADDRESS_CR_MASK; in ENET_StartSMIWrite()
1037 uint32_t reg = base->MAC_MDIO_ADDRESS & ENET_MAC_MDIO_ADDRESS_CR_MASK; in ENET_StartSMIRead()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h18592 #define ENET_MAC_MDIO_ADDRESS_CR_MASK (0xF00U) macro
18595 … (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_CR_SHIFT)) & ENET_MAC_MDIO_ADDRESS_CR_MASK)
DMCXN546_cm33_core1.h18592 #define ENET_MAC_MDIO_ADDRESS_CR_MASK (0xF00U) macro
18595 … (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_CR_SHIFT)) & ENET_MAC_MDIO_ADDRESS_CR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h18592 #define ENET_MAC_MDIO_ADDRESS_CR_MASK (0xF00U) macro
18595 … (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_CR_SHIFT)) & ENET_MAC_MDIO_ADDRESS_CR_MASK)
DMCXN547_cm33_core1.h18592 #define ENET_MAC_MDIO_ADDRESS_CR_MASK (0xF00U) macro
18595 … (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_CR_SHIFT)) & ENET_MAC_MDIO_ADDRESS_CR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h18638 #define ENET_MAC_MDIO_ADDRESS_CR_MASK (0xF00U) macro
18641 … (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_CR_SHIFT)) & ENET_MAC_MDIO_ADDRESS_CR_MASK)
DMCXN947_cm33_core0.h18638 #define ENET_MAC_MDIO_ADDRESS_CR_MASK (0xF00U) macro
18641 … (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_CR_SHIFT)) & ENET_MAC_MDIO_ADDRESS_CR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h18638 #define ENET_MAC_MDIO_ADDRESS_CR_MASK (0xF00U) macro
18641 … (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_CR_SHIFT)) & ENET_MAC_MDIO_ADDRESS_CR_MASK)
DMCXN946_cm33_core1.h18638 #define ENET_MAC_MDIO_ADDRESS_CR_MASK (0xF00U) macro
18641 … (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDRESS_CR_SHIFT)) & ENET_MAC_MDIO_ADDRESS_CR_MASK)