1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_ENETC_PSEUDO_MAC_PORT2.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_ENETC_PSEUDO_MAC_PORT2 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_ENETC_PSEUDO_MAC_PORT2_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_ENETC_PSEUDO_MAC_PORT2_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- ENETC_PSEUDO_MAC_PORT2 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup ENETC_PSEUDO_MAC_PORT2_Peripheral_Access_Layer ENETC_PSEUDO_MAC_PORT2 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** ENETC_PSEUDO_MAC_PORT2 - Size of Registers Arrays */ 72 #define ENETC_PSEUDO_MAC_PORT2_PPMROCR_COUNT 2u 73 #define ENETC_PSEUDO_MAC_PORT2_PPMRUFCR_COUNT 2u 74 #define ENETC_PSEUDO_MAC_PORT2_PPMRMFCR_COUNT 2u 75 #define ENETC_PSEUDO_MAC_PORT2_PPMRBFCR_COUNT 2u 76 #define ENETC_PSEUDO_MAC_PORT2_PPMTOCR_COUNT 2u 77 #define ENETC_PSEUDO_MAC_PORT2_PPMTUFCR_COUNT 2u 78 #define ENETC_PSEUDO_MAC_PORT2_PPMTMFCR_COUNT 2u 79 #define ENETC_PSEUDO_MAC_PORT2_PPMTBFCR_COUNT 2u 80 81 /** ENETC_PSEUDO_MAC_PORT2 - Register Layout Typedef */ 82 typedef struct { 83 __I uint32_t PPMSR; /**< Port pseudo MAC status register, offset: 0x0 */ 84 uint8_t RESERVED_0[12]; 85 __IO uint32_t PPMCR; /**< Port pseudo MAC configuration register, offset: 0x10 */ 86 uint8_t RESERVED_1[108]; 87 __I uint32_t PPMROCR[ENETC_PSEUDO_MAC_PORT2_PPMROCR_COUNT]; /**< Port pseudo MAC receive octets counter, array offset: 0x80, array step: 0x4 */ 88 __I uint32_t PPMRUFCR[ENETC_PSEUDO_MAC_PORT2_PPMRUFCR_COUNT]; /**< Port pseudo MAC receive unicast frame counter register, array offset: 0x88, array step: 0x4 */ 89 __I uint32_t PPMRMFCR[ENETC_PSEUDO_MAC_PORT2_PPMRMFCR_COUNT]; /**< Port pseudo MAC receive multicast frame counter register, array offset: 0x90, array step: 0x4 */ 90 __I uint32_t PPMRBFCR[ENETC_PSEUDO_MAC_PORT2_PPMRBFCR_COUNT]; /**< Port pseudo MAC receive broadcast frame counter register, array offset: 0x98, array step: 0x4 */ 91 uint8_t RESERVED_2[32]; 92 __I uint32_t PPMTOCR[ENETC_PSEUDO_MAC_PORT2_PPMTOCR_COUNT]; /**< Port pseudo MAC transmit octets counter, array offset: 0xC0, array step: 0x4 */ 93 __I uint32_t PPMTUFCR[ENETC_PSEUDO_MAC_PORT2_PPMTUFCR_COUNT]; /**< Port pseudo MAC transmit unicast frame counter register, array offset: 0xC8, array step: 0x4 */ 94 __I uint32_t PPMTMFCR[ENETC_PSEUDO_MAC_PORT2_PPMTMFCR_COUNT]; /**< Port pseudo MAC transmit multicast frame counter register, array offset: 0xD0, array step: 0x4 */ 95 __I uint32_t PPMTBFCR[ENETC_PSEUDO_MAC_PORT2_PPMTBFCR_COUNT]; /**< Port pseudo MAC transmit broadcast frame counter register, array offset: 0xD8, array step: 0x4 */ 96 } ENETC_PSEUDO_MAC_PORT2_Type, *ENETC_PSEUDO_MAC_PORT2_MemMapPtr; 97 98 /** Number of instances of the ENETC_PSEUDO_MAC_PORT2 module. */ 99 #define ENETC_PSEUDO_MAC_PORT2_INSTANCE_COUNT (1u) 100 101 /* ENETC_PSEUDO_MAC_PORT2 - Peripheral instance base addresses */ 102 /** Peripheral NETC__ENETC0_PSEUDO_MAC_PORT base address */ 103 #define IP_NETC__ENETC0_PSEUDO_MAC_PORT_BASE (0x74B15000u) 104 /** Peripheral NETC__ENETC0_PSEUDO_MAC_PORT base pointer */ 105 #define IP_NETC__ENETC0_PSEUDO_MAC_PORT ((ENETC_PSEUDO_MAC_PORT2_Type *)IP_NETC__ENETC0_PSEUDO_MAC_PORT_BASE) 106 /** Array initializer of ENETC_PSEUDO_MAC_PORT2 peripheral base addresses */ 107 #define IP_ENETC_PSEUDO_MAC_PORT2_BASE_ADDRS { IP_NETC__ENETC0_PSEUDO_MAC_PORT_BASE } 108 /** Array initializer of ENETC_PSEUDO_MAC_PORT2 peripheral base pointers */ 109 #define IP_ENETC_PSEUDO_MAC_PORT2_BASE_PTRS { IP_NETC__ENETC0_PSEUDO_MAC_PORT } 110 111 /* ---------------------------------------------------------------------------- 112 -- ENETC_PSEUDO_MAC_PORT2 Register Masks 113 ---------------------------------------------------------------------------- */ 114 115 /*! 116 * @addtogroup ENETC_PSEUDO_MAC_PORT2_Register_Masks ENETC_PSEUDO_MAC_PORT2 Register Masks 117 * @{ 118 */ 119 120 /*! @name PPMSR - Port pseudo MAC status register */ 121 /*! @{ */ 122 123 #define ENETC_PSEUDO_MAC_PORT2_PPMSR_LSTATE_MASK (0x1U) 124 #define ENETC_PSEUDO_MAC_PORT2_PPMSR_LSTATE_SHIFT (0U) 125 #define ENETC_PSEUDO_MAC_PORT2_PPMSR_LSTATE_WIDTH (1U) 126 #define ENETC_PSEUDO_MAC_PORT2_PPMSR_LSTATE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PSEUDO_MAC_PORT2_PPMSR_LSTATE_SHIFT)) & ENETC_PSEUDO_MAC_PORT2_PPMSR_LSTATE_MASK) 127 128 #define ENETC_PSEUDO_MAC_PORT2_PPMSR_RSTATE_MASK (0x100U) 129 #define ENETC_PSEUDO_MAC_PORT2_PPMSR_RSTATE_SHIFT (8U) 130 #define ENETC_PSEUDO_MAC_PORT2_PPMSR_RSTATE_WIDTH (1U) 131 #define ENETC_PSEUDO_MAC_PORT2_PPMSR_RSTATE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PSEUDO_MAC_PORT2_PPMSR_RSTATE_SHIFT)) & ENETC_PSEUDO_MAC_PORT2_PPMSR_RSTATE_MASK) 132 /*! @} */ 133 134 /*! @name PPMCR - Port pseudo MAC configuration register */ 135 /*! @{ */ 136 137 #define ENETC_PSEUDO_MAC_PORT2_PPMCR_TXPAD_MASK (0x10000U) 138 #define ENETC_PSEUDO_MAC_PORT2_PPMCR_TXPAD_SHIFT (16U) 139 #define ENETC_PSEUDO_MAC_PORT2_PPMCR_TXPAD_WIDTH (1U) 140 #define ENETC_PSEUDO_MAC_PORT2_PPMCR_TXPAD(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PSEUDO_MAC_PORT2_PPMCR_TXPAD_SHIFT)) & ENETC_PSEUDO_MAC_PORT2_PPMCR_TXPAD_MASK) 141 /*! @} */ 142 143 /*! @name PPMROCR - Port pseudo MAC receive octets counter */ 144 /*! @{ */ 145 146 #define ENETC_PSEUDO_MAC_PORT2_PPMROCR_ROCT_MASK (0xFFFFFFFFU) 147 #define ENETC_PSEUDO_MAC_PORT2_PPMROCR_ROCT_SHIFT (0U) 148 #define ENETC_PSEUDO_MAC_PORT2_PPMROCR_ROCT_WIDTH (32U) 149 #define ENETC_PSEUDO_MAC_PORT2_PPMROCR_ROCT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PSEUDO_MAC_PORT2_PPMROCR_ROCT_SHIFT)) & ENETC_PSEUDO_MAC_PORT2_PPMROCR_ROCT_MASK) 150 /*! @} */ 151 152 /*! @name PPMRUFCR - Port pseudo MAC receive unicast frame counter register */ 153 /*! @{ */ 154 155 #define ENETC_PSEUDO_MAC_PORT2_PPMRUFCR_RUCA_MASK (0xFFFFFFFFU) 156 #define ENETC_PSEUDO_MAC_PORT2_PPMRUFCR_RUCA_SHIFT (0U) 157 #define ENETC_PSEUDO_MAC_PORT2_PPMRUFCR_RUCA_WIDTH (32U) 158 #define ENETC_PSEUDO_MAC_PORT2_PPMRUFCR_RUCA(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PSEUDO_MAC_PORT2_PPMRUFCR_RUCA_SHIFT)) & ENETC_PSEUDO_MAC_PORT2_PPMRUFCR_RUCA_MASK) 159 /*! @} */ 160 161 /*! @name PPMRMFCR - Port pseudo MAC receive multicast frame counter register */ 162 /*! @{ */ 163 164 #define ENETC_PSEUDO_MAC_PORT2_PPMRMFCR_RMCA_MASK (0xFFFFFFFFU) 165 #define ENETC_PSEUDO_MAC_PORT2_PPMRMFCR_RMCA_SHIFT (0U) 166 #define ENETC_PSEUDO_MAC_PORT2_PPMRMFCR_RMCA_WIDTH (32U) 167 #define ENETC_PSEUDO_MAC_PORT2_PPMRMFCR_RMCA(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PSEUDO_MAC_PORT2_PPMRMFCR_RMCA_SHIFT)) & ENETC_PSEUDO_MAC_PORT2_PPMRMFCR_RMCA_MASK) 168 /*! @} */ 169 170 /*! @name PPMRBFCR - Port pseudo MAC receive broadcast frame counter register */ 171 /*! @{ */ 172 173 #define ENETC_PSEUDO_MAC_PORT2_PPMRBFCR_RBCA_MASK (0xFFFFFFFFU) 174 #define ENETC_PSEUDO_MAC_PORT2_PPMRBFCR_RBCA_SHIFT (0U) 175 #define ENETC_PSEUDO_MAC_PORT2_PPMRBFCR_RBCA_WIDTH (32U) 176 #define ENETC_PSEUDO_MAC_PORT2_PPMRBFCR_RBCA(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PSEUDO_MAC_PORT2_PPMRBFCR_RBCA_SHIFT)) & ENETC_PSEUDO_MAC_PORT2_PPMRBFCR_RBCA_MASK) 177 /*! @} */ 178 179 /*! @name PPMTOCR - Port pseudo MAC transmit octets counter */ 180 /*! @{ */ 181 182 #define ENETC_PSEUDO_MAC_PORT2_PPMTOCR_TOCT_MASK (0xFFFFFFFFU) 183 #define ENETC_PSEUDO_MAC_PORT2_PPMTOCR_TOCT_SHIFT (0U) 184 #define ENETC_PSEUDO_MAC_PORT2_PPMTOCR_TOCT_WIDTH (32U) 185 #define ENETC_PSEUDO_MAC_PORT2_PPMTOCR_TOCT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PSEUDO_MAC_PORT2_PPMTOCR_TOCT_SHIFT)) & ENETC_PSEUDO_MAC_PORT2_PPMTOCR_TOCT_MASK) 186 /*! @} */ 187 188 /*! @name PPMTUFCR - Port pseudo MAC transmit unicast frame counter register */ 189 /*! @{ */ 190 191 #define ENETC_PSEUDO_MAC_PORT2_PPMTUFCR_TUCA_MASK (0xFFFFFFFFU) 192 #define ENETC_PSEUDO_MAC_PORT2_PPMTUFCR_TUCA_SHIFT (0U) 193 #define ENETC_PSEUDO_MAC_PORT2_PPMTUFCR_TUCA_WIDTH (32U) 194 #define ENETC_PSEUDO_MAC_PORT2_PPMTUFCR_TUCA(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PSEUDO_MAC_PORT2_PPMTUFCR_TUCA_SHIFT)) & ENETC_PSEUDO_MAC_PORT2_PPMTUFCR_TUCA_MASK) 195 /*! @} */ 196 197 /*! @name PPMTMFCR - Port pseudo MAC transmit multicast frame counter register */ 198 /*! @{ */ 199 200 #define ENETC_PSEUDO_MAC_PORT2_PPMTMFCR_TMCA_MASK (0xFFFFFFFFU) 201 #define ENETC_PSEUDO_MAC_PORT2_PPMTMFCR_TMCA_SHIFT (0U) 202 #define ENETC_PSEUDO_MAC_PORT2_PPMTMFCR_TMCA_WIDTH (32U) 203 #define ENETC_PSEUDO_MAC_PORT2_PPMTMFCR_TMCA(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PSEUDO_MAC_PORT2_PPMTMFCR_TMCA_SHIFT)) & ENETC_PSEUDO_MAC_PORT2_PPMTMFCR_TMCA_MASK) 204 /*! @} */ 205 206 /*! @name PPMTBFCR - Port pseudo MAC transmit broadcast frame counter register */ 207 /*! @{ */ 208 209 #define ENETC_PSEUDO_MAC_PORT2_PPMTBFCR_TBCA_MASK (0xFFFFFFFFU) 210 #define ENETC_PSEUDO_MAC_PORT2_PPMTBFCR_TBCA_SHIFT (0U) 211 #define ENETC_PSEUDO_MAC_PORT2_PPMTBFCR_TBCA_WIDTH (32U) 212 #define ENETC_PSEUDO_MAC_PORT2_PPMTBFCR_TBCA(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PSEUDO_MAC_PORT2_PPMTBFCR_TBCA_SHIFT)) & ENETC_PSEUDO_MAC_PORT2_PPMTBFCR_TBCA_MASK) 213 /*! @} */ 214 215 /*! 216 * @} 217 */ /* end of group ENETC_PSEUDO_MAC_PORT2_Register_Masks */ 218 219 /*! 220 * @} 221 */ /* end of group ENETC_PSEUDO_MAC_PORT2_Peripheral_Access_Layer */ 222 223 #endif /* #if !defined(S32Z2_ENETC_PSEUDO_MAC_PORT2_H_) */ 224
