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Searched refs:EMVSIM_TX_GETU_GETU_MASK (Results 1 – 25 of 30) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h4921 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
4929 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h4921 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
4929 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/
DK32L3A60_cm4.h6025 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
6033 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
DK32L3A60_cm0plus.h5078 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
5086 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h9391 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
9399 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h9385 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
9393 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h16533 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
16536 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
DMCXN546_cm33_core1.h16533 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
16536 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h16533 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
16536 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
DMCXN547_cm33_core1.h16533 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
16536 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h31734 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
31737 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
DMIMXRT1175_cm7.h31736 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
31739 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h31424 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
31427 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
DMIMXRT1165_cm4.h31422 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
31425 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h31736 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
31739 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h16579 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
16582 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
DMCXN947_cm33_core0.h16579 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
16582 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h16579 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
16582 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
DMCXN946_cm33_core1.h16579 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
16582 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_ca53.h23652 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
23660 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h33427 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
33430 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
DMIMXRT1166_cm7.h33429 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
33432 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h33736 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
33739 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
DMIMXRT1173_cm7.h33738 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
33741 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h33741 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) macro
33744 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)

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