Home
last modified time | relevance | path

Searched refs:EMVSIM_INT_MASK_PEF_IM_MASK (Results 1 – 25 of 30) sorted by relevance

12

/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h4579 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
4585 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h4579 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
4585 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/
DK32L3A60_cm4.h5683 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
5689 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
DK32L3A60_cm0plus.h4736 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
4742 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h9096 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
9102 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h9090 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
9096 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/
DMCXN546_cm33_core0.h16199 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
16205 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
DMCXN546_cm33_core1.h16199 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
16205 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN547/
DMCXN547_cm33_core0.h16199 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
16205 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
DMCXN547_cm33_core1.h16199 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
16205 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h31400 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
31406 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
DMIMXRT1175_cm7.h31402 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
31408 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h31090 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
31096 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
DMIMXRT1165_cm4.h31088 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
31094 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h31402 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
31408 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h16245 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
16251 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
DMCXN947_cm33_core0.h16245 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
16251 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h16245 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
16251 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
DMCXN946_cm33_core1.h16245 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
16251 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_ca53.h23310 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
23316 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h33093 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
33099 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
DMIMXRT1166_cm7.h33095 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
33101 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h33402 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
33408 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
DMIMXRT1173_cm7.h33404 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
33410 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h33407 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) macro
33413 … (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)

12