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Searched refs:EMIOS_ICU_IP_INIT_CADR_U32 (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-latest/s32/drivers/s32k3/Icu/src/
DEmios_Icu_Ip.c557 …ate[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].maxCounterValue = EMIOS_ICU_IP_INIT_CADR_U32; in Emios_Icu_Ip_Init()
1019 s_emiosBase[instance]->CH.UC[hwChannel].A = EMIOS_ICU_IP_INIT_CADR_U32; in Emios_Icu_Ip_StartTimestamp()
1170 s_emiosBase[instance]->CH.UC[hwChannel].A = EMIOS_ICU_IP_INIT_CADR_U32; in Emios_Icu_Ip_ResetEdgeCount()
1201 s_emiosBase[instance]->CH.UC[hwChannel].A = EMIOS_ICU_IP_INIT_CADR_U32; in Emios_Icu_Ip_EnableEdgeCount()
1254 …ate[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].maxCounterValue = EMIOS_ICU_IP_INIT_CADR_U32; in Emios_Icu_Ip_DisableEdgeCount()
1440 s_emiosBase[instance]->CH.UC[hwChannel].A = EMIOS_ICU_IP_INIT_CADR_U32; in Emios_Icu_Ip_StartSignalMeasurement()
/hal_nxp-latest/s32/drivers/s32ze/Icu/src/
DEmios_Icu_Ip.c607 …ate[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].maxCounterValue = EMIOS_ICU_IP_INIT_CADR_U32; in Emios_Icu_Ip_Init()
1147 s_emiosBase[instance]->CH.UC[hwChannel].A = EMIOS_ICU_IP_INIT_CADR_U32; in Emios_Icu_Ip_StartTimestamp()
1298 s_emiosBase[instance]->CH.UC[hwChannel].A = EMIOS_ICU_IP_INIT_CADR_U32; in Emios_Icu_Ip_ResetEdgeCount()
1329 s_emiosBase[instance]->CH.UC[hwChannel].A = EMIOS_ICU_IP_INIT_CADR_U32; in Emios_Icu_Ip_EnableEdgeCount()
1382 …ate[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].maxCounterValue = EMIOS_ICU_IP_INIT_CADR_U32; in Emios_Icu_Ip_DisableEdgeCount()
1568 s_emiosBase[instance]->CH.UC[hwChannel].A = EMIOS_ICU_IP_INIT_CADR_U32; in Emios_Icu_Ip_StartSignalMeasurement()
/hal_nxp-latest/s32/drivers/s32k3/Icu/include/
DEmios_Icu_Ip_Types.h101 #define EMIOS_ICU_IP_INIT_CADR_U32 ((uint32)EMIOS_ICU_IP_COUNTER_MASK) macro
/hal_nxp-latest/s32/drivers/s32ze/Icu/include/
DEmios_Icu_Ip_Types.h101 #define EMIOS_ICU_IP_INIT_CADR_U32 ((uint32)EMIOS_ICU_IP_COUNTER_MASK) macro