1 /*
2  * Copyright 2022 NXP
3  * All rights reserved.
4  *
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 #ifndef FSL_EIM_H_
10 #define FSL_EIM_H_
11 
12 #include "fsl_common.h"
13 
14 /*!
15  * @addtogroup eim
16  * @{
17  */
18 
19 /******************************************************************************
20  * Definitions.
21  *****************************************************************************/
22 
23 /*! @name Driver version */
24 /*! @{ */
25 /*! @brief Driver version. */
26 #define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
27 /*! @} */
28 
29 /*******************************************************************************
30  * APIs
31  ******************************************************************************/
32 
33 #if defined(__cplusplus)
34 extern "C" {
35 #endif
36 
37 /*!
38  * @brief EIM module initialization function.
39  *
40  * @param base EIM base address.
41  */
42 void EIM_Init(EIM_Type *base);
43 
44 /*!
45  * @brief De-initializes the EIM.
46  *
47  */
48 void EIM_Deinit(EIM_Type *base);
49 
50 /*! @} */
51 
52 /*!
53  * @name functional
54  * @{
55  */
56 
57 /*!
58  * @brief EIM module enable global error injection.
59  *
60  * @param base EIM base address.
61  * @param mask The interrupts to enable.
62  */
EIM_EnableGlobalErrorInjection(EIM_Type * base,bool enable)63 static inline void EIM_EnableGlobalErrorInjection(EIM_Type *base, bool enable)
64 {
65     if (enable)
66     {
67         base->EIMCR = EIM_EIMCR_GEIEN_MASK;
68     }
69     else
70     {
71         base->EIMCR = ~EIM_EIMCR_GEIEN_MASK;
72     }
73 }
74 
75 /*!
76  * @brief EIM module enable error injection for memory channel n, this function enables the corresponding error
77  * injection channel. The Global Error Injection Enable function must also be called to enable error injection.
78  *
79  * @param base EIM base address.
80  * @param mask The interrupts to enable. Refer to "_eim_error_injection_channel_enable" enumeration.
81  */
EIM_EnableErrorInjectionChannels(EIM_Type * base,uint32_t mask)82 static inline void EIM_EnableErrorInjectionChannels(EIM_Type *base, uint32_t mask)
83 {
84     base->EICHEN |= mask;
85 }
86 
87 /*!
88  * @brief EIM module disable error injection for memory channel n.
89  *
90  * @param base EIM base address.
91  * @param mask The interrupts to enable. Refer to "_eim_error_injection_channel_enable" enumeration.
92  */
EIM_DisableErrorInjectionChannels(EIM_Type * base,uint32_t mask)93 static inline void EIM_DisableErrorInjectionChannels(EIM_Type *base, uint32_t mask)
94 {
95     base->EICHEN &= ~mask;
96 }
97 
98 /*!
99  * @brief EIM module inject checkbit error for memory channel n, an attempt to invert more than 2 bits in one operation
100  * might result in undefined behavior.
101  *
102  * @param base EIM base address.
103  * @param channel memory channel.
104  * @param mask The interrupts to enable.
105  */
106 void EIM_InjectCheckBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask);
107 
108 /*!
109  * @brief EIM module get checkbit mask for memory channel n.
110  *
111  * @param base EIM base address.
112  * @param channel memory channel.
113  * @retval return checkbit mask.
114  */
115 uint8_t EIM_GetCheckBitMask(EIM_Type *base, eim_memory_channel_t channel);
116 
117 /*!
118  * @brief EIM module inject databit error for memory channel n, an attempt to invert more than 2 bits in one operation
119  * might result in undefined behavior.
120  *
121  * @param base EIM base address.
122  * @param channel memory channel.
123  * @param mask The interrupts to enable.
124  */
125 void EIM_InjectDataBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask);
126 
127 /*!
128  * @brief EIM module get databit mask for memory channel n.
129  *
130  * @param base EIM base address.
131  * @param channel memory channel.
132  * @retval return checkbit mask.
133  */
134 uint32_t EIM_GetDataBitMask(EIM_Type *base, eim_memory_channel_t channel);
135 
136 /*! @}*/
137 
138 #if defined(__cplusplus)
139 }
140 #endif
141 
142 /*! @}*/
143 
144 #endif
145