1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_EDMA4_TCD.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_EDMA4_TCD 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_EDMA4_TCD_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_EDMA4_TCD_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- EDMA4_TCD Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup EDMA4_TCD_Peripheral_Access_Layer EDMA4_TCD Peripheral Access Layer 68 * @{ 69 */ 70 71 /** EDMA4_TCD - Size of Registers Arrays */ 72 #define EDMA4_TCD_TCD_COUNT 32u 73 74 /** EDMA4_TCD - Register Layout Typedef */ 75 typedef struct { 76 struct EDMA4_TCD_TCD { /* offset: 0x0, array step: 0x10000 */ 77 __IO uint32_t CH_CSR; /**< Channel Control and Status Register, array offset: 0x0, array step: 0x10000 */ 78 __IO uint32_t CH_ES; /**< Channel Error Status Register, array offset: 0x4, array step: 0x10000 */ 79 __IO uint32_t CH_INT; /**< Channel Interrupt Status Register, array offset: 0x8, array step: 0x10000 */ 80 __IO uint32_t CH_SBR; /**< Channel System Bus Register, array offset: 0xC, array step: 0x10000 */ 81 __IO uint32_t CH_PRI; /**< Channel Priority Register, array offset: 0x10, array step: 0x10000 */ 82 uint8_t RESERVED_0[4]; 83 __IO uint16_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x18, array step: 0x10000 */ 84 uint8_t RESERVED_1[6]; 85 __IO uint32_t SADDR; /**< TCD Source Address Register, array offset: 0x20, array step: 0x10000 */ 86 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset Register, array offset: 0x24, array step: 0x10000 */ 87 __IO uint16_t ATTR; /**< TCD Transfer Attributes Register, array offset: 0x26, array step: 0x10000 */ 88 union { /* offset: 0x28, array step: 0x10000 */ 89 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Transfer Size without Minor Loop Offsets Register, array offset: 0x28, array step: 0x10000 */ 90 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets Register, array offset: 0x28, array step: 0x10000 */ 91 } NBYTES; 92 __IO uint32_t SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address Register, array offset: 0x2C, array step: 0x10000 */ 93 __IO uint32_t DADDR; /**< TCD Destination Address Register, array offset: 0x30, array step: 0x10000 */ 94 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset Register, array offset: 0x34, array step: 0x10000 */ 95 union { /* offset: 0x36, array step: 0x10000 */ 96 __IO uint16_t CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) Register, array offset: 0x36, array step: 0x10000 */ 97 __IO uint16_t CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) Register, array offset: 0x36, array step: 0x10000 */ 98 } CITER; 99 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address Register, array offset: 0x38, array step: 0x10000 */ 100 __IO uint16_t CSR; /**< TCD Control and Status Register, array offset: 0x3C, array step: 0x10000 */ 101 union { /* offset: 0x3E, array step: 0x10000 */ 102 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) Register, array offset: 0x3E, array step: 0x10000 */ 103 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) Register, array offset: 0x3E, array step: 0x10000 */ 104 } BITER; 105 uint8_t RESERVED_2[65472]; 106 } TCD[EDMA4_TCD_TCD_COUNT]; 107 } EDMA4_TCD_Type, *EDMA4_TCD_MemMapPtr; 108 109 /** Number of instances of the EDMA4_TCD module. */ 110 #define EDMA4_TCD_INSTANCE_COUNT (1u) 111 112 /* EDMA4_TCD - Peripheral instance base addresses */ 113 /** Peripheral EDMA_3_TCD base address */ 114 #define IP_EDMA_3_TCD_BASE (0x41E00000u) 115 /** Peripheral EDMA_3_TCD base pointer */ 116 #define IP_EDMA_3_TCD ((EDMA4_TCD_Type *)IP_EDMA_3_TCD_BASE) 117 /** Array initializer of EDMA4_TCD peripheral base addresses */ 118 #define IP_EDMA4_TCD_BASE_ADDRS { IP_EDMA_3_TCD_BASE } 119 /** Array initializer of EDMA4_TCD peripheral base pointers */ 120 #define IP_EDMA4_TCD_BASE_PTRS { IP_EDMA_3_TCD } 121 122 /* ---------------------------------------------------------------------------- 123 -- EDMA4_TCD Register Masks 124 ---------------------------------------------------------------------------- */ 125 126 /*! 127 * @addtogroup EDMA4_TCD_Register_Masks EDMA4_TCD Register Masks 128 * @{ 129 */ 130 131 /*! @name CH_CSR - Channel Control and Status Register */ 132 /*! @{ */ 133 134 #define EDMA4_TCD_CH_CSR_ERQ_MASK (0x1U) 135 #define EDMA4_TCD_CH_CSR_ERQ_SHIFT (0U) 136 #define EDMA4_TCD_CH_CSR_ERQ_WIDTH (1U) 137 #define EDMA4_TCD_CH_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_CSR_ERQ_SHIFT)) & EDMA4_TCD_CH_CSR_ERQ_MASK) 138 139 #define EDMA4_TCD_CH_CSR_EARQ_MASK (0x2U) 140 #define EDMA4_TCD_CH_CSR_EARQ_SHIFT (1U) 141 #define EDMA4_TCD_CH_CSR_EARQ_WIDTH (1U) 142 #define EDMA4_TCD_CH_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_CSR_EARQ_SHIFT)) & EDMA4_TCD_CH_CSR_EARQ_MASK) 143 144 #define EDMA4_TCD_CH_CSR_EEI_MASK (0x4U) 145 #define EDMA4_TCD_CH_CSR_EEI_SHIFT (2U) 146 #define EDMA4_TCD_CH_CSR_EEI_WIDTH (1U) 147 #define EDMA4_TCD_CH_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_CSR_EEI_SHIFT)) & EDMA4_TCD_CH_CSR_EEI_MASK) 148 149 #define EDMA4_TCD_CH_CSR_SWAP_MASK (0xF000U) 150 #define EDMA4_TCD_CH_CSR_SWAP_SHIFT (12U) 151 #define EDMA4_TCD_CH_CSR_SWAP_WIDTH (4U) 152 #define EDMA4_TCD_CH_CSR_SWAP(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_CSR_SWAP_SHIFT)) & EDMA4_TCD_CH_CSR_SWAP_MASK) 153 154 #define EDMA4_TCD_CH_CSR_SIGNEXT_MASK (0x3F0000U) 155 #define EDMA4_TCD_CH_CSR_SIGNEXT_SHIFT (16U) 156 #define EDMA4_TCD_CH_CSR_SIGNEXT_WIDTH (6U) 157 #define EDMA4_TCD_CH_CSR_SIGNEXT(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_CSR_SIGNEXT_SHIFT)) & EDMA4_TCD_CH_CSR_SIGNEXT_MASK) 158 159 #define EDMA4_TCD_CH_CSR_DONE_MASK (0x40000000U) 160 #define EDMA4_TCD_CH_CSR_DONE_SHIFT (30U) 161 #define EDMA4_TCD_CH_CSR_DONE_WIDTH (1U) 162 #define EDMA4_TCD_CH_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_CSR_DONE_SHIFT)) & EDMA4_TCD_CH_CSR_DONE_MASK) 163 164 #define EDMA4_TCD_CH_CSR_ACTIVE_MASK (0x80000000U) 165 #define EDMA4_TCD_CH_CSR_ACTIVE_SHIFT (31U) 166 #define EDMA4_TCD_CH_CSR_ACTIVE_WIDTH (1U) 167 #define EDMA4_TCD_CH_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_CSR_ACTIVE_SHIFT)) & EDMA4_TCD_CH_CSR_ACTIVE_MASK) 168 /*! @} */ 169 170 /*! @name CH_ES - Channel Error Status Register */ 171 /*! @{ */ 172 173 #define EDMA4_TCD_CH_ES_DBE_MASK (0x1U) 174 #define EDMA4_TCD_CH_ES_DBE_SHIFT (0U) 175 #define EDMA4_TCD_CH_ES_DBE_WIDTH (1U) 176 #define EDMA4_TCD_CH_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_ES_DBE_SHIFT)) & EDMA4_TCD_CH_ES_DBE_MASK) 177 178 #define EDMA4_TCD_CH_ES_SBE_MASK (0x2U) 179 #define EDMA4_TCD_CH_ES_SBE_SHIFT (1U) 180 #define EDMA4_TCD_CH_ES_SBE_WIDTH (1U) 181 #define EDMA4_TCD_CH_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_ES_SBE_SHIFT)) & EDMA4_TCD_CH_ES_SBE_MASK) 182 183 #define EDMA4_TCD_CH_ES_SGE_MASK (0x4U) 184 #define EDMA4_TCD_CH_ES_SGE_SHIFT (2U) 185 #define EDMA4_TCD_CH_ES_SGE_WIDTH (1U) 186 #define EDMA4_TCD_CH_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_ES_SGE_SHIFT)) & EDMA4_TCD_CH_ES_SGE_MASK) 187 188 #define EDMA4_TCD_CH_ES_NCE_MASK (0x8U) 189 #define EDMA4_TCD_CH_ES_NCE_SHIFT (3U) 190 #define EDMA4_TCD_CH_ES_NCE_WIDTH (1U) 191 #define EDMA4_TCD_CH_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_ES_NCE_SHIFT)) & EDMA4_TCD_CH_ES_NCE_MASK) 192 193 #define EDMA4_TCD_CH_ES_DOE_MASK (0x10U) 194 #define EDMA4_TCD_CH_ES_DOE_SHIFT (4U) 195 #define EDMA4_TCD_CH_ES_DOE_WIDTH (1U) 196 #define EDMA4_TCD_CH_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_ES_DOE_SHIFT)) & EDMA4_TCD_CH_ES_DOE_MASK) 197 198 #define EDMA4_TCD_CH_ES_DAE_MASK (0x20U) 199 #define EDMA4_TCD_CH_ES_DAE_SHIFT (5U) 200 #define EDMA4_TCD_CH_ES_DAE_WIDTH (1U) 201 #define EDMA4_TCD_CH_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_ES_DAE_SHIFT)) & EDMA4_TCD_CH_ES_DAE_MASK) 202 203 #define EDMA4_TCD_CH_ES_SOE_MASK (0x40U) 204 #define EDMA4_TCD_CH_ES_SOE_SHIFT (6U) 205 #define EDMA4_TCD_CH_ES_SOE_WIDTH (1U) 206 #define EDMA4_TCD_CH_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_ES_SOE_SHIFT)) & EDMA4_TCD_CH_ES_SOE_MASK) 207 208 #define EDMA4_TCD_CH_ES_SAE_MASK (0x80U) 209 #define EDMA4_TCD_CH_ES_SAE_SHIFT (7U) 210 #define EDMA4_TCD_CH_ES_SAE_WIDTH (1U) 211 #define EDMA4_TCD_CH_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_ES_SAE_SHIFT)) & EDMA4_TCD_CH_ES_SAE_MASK) 212 213 #define EDMA4_TCD_CH_ES_ERR_MASK (0x80000000U) 214 #define EDMA4_TCD_CH_ES_ERR_SHIFT (31U) 215 #define EDMA4_TCD_CH_ES_ERR_WIDTH (1U) 216 #define EDMA4_TCD_CH_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_ES_ERR_SHIFT)) & EDMA4_TCD_CH_ES_ERR_MASK) 217 /*! @} */ 218 219 /*! @name CH_INT - Channel Interrupt Status Register */ 220 /*! @{ */ 221 222 #define EDMA4_TCD_CH_INT_INT_MASK (0x1U) 223 #define EDMA4_TCD_CH_INT_INT_SHIFT (0U) 224 #define EDMA4_TCD_CH_INT_INT_WIDTH (1U) 225 #define EDMA4_TCD_CH_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_INT_INT_SHIFT)) & EDMA4_TCD_CH_INT_INT_MASK) 226 /*! @} */ 227 228 /*! @name CH_SBR - Channel System Bus Register */ 229 /*! @{ */ 230 231 #define EDMA4_TCD_CH_SBR_MID_MASK (0x3FU) 232 #define EDMA4_TCD_CH_SBR_MID_SHIFT (0U) 233 #define EDMA4_TCD_CH_SBR_MID_WIDTH (6U) 234 #define EDMA4_TCD_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_SBR_MID_SHIFT)) & EDMA4_TCD_CH_SBR_MID_MASK) 235 236 #define EDMA4_TCD_CH_SBR_INSTR_MASK (0x2000U) 237 #define EDMA4_TCD_CH_SBR_INSTR_SHIFT (13U) 238 #define EDMA4_TCD_CH_SBR_INSTR_WIDTH (1U) 239 #define EDMA4_TCD_CH_SBR_INSTR(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_SBR_INSTR_SHIFT)) & EDMA4_TCD_CH_SBR_INSTR_MASK) 240 241 #define EDMA4_TCD_CH_SBR_SEC_MASK (0x4000U) 242 #define EDMA4_TCD_CH_SBR_SEC_SHIFT (14U) 243 #define EDMA4_TCD_CH_SBR_SEC_WIDTH (1U) 244 #define EDMA4_TCD_CH_SBR_SEC(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_SBR_SEC_SHIFT)) & EDMA4_TCD_CH_SBR_SEC_MASK) 245 246 #define EDMA4_TCD_CH_SBR_PAL_MASK (0x8000U) 247 #define EDMA4_TCD_CH_SBR_PAL_SHIFT (15U) 248 #define EDMA4_TCD_CH_SBR_PAL_WIDTH (1U) 249 #define EDMA4_TCD_CH_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_SBR_PAL_SHIFT)) & EDMA4_TCD_CH_SBR_PAL_MASK) 250 251 #define EDMA4_TCD_CH_SBR_EMI_MASK (0x10000U) 252 #define EDMA4_TCD_CH_SBR_EMI_SHIFT (16U) 253 #define EDMA4_TCD_CH_SBR_EMI_WIDTH (1U) 254 #define EDMA4_TCD_CH_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_SBR_EMI_SHIFT)) & EDMA4_TCD_CH_SBR_EMI_MASK) 255 256 #define EDMA4_TCD_CH_SBR_ATTR_MASK (0x7E0000U) 257 #define EDMA4_TCD_CH_SBR_ATTR_SHIFT (17U) 258 #define EDMA4_TCD_CH_SBR_ATTR_WIDTH (6U) 259 #define EDMA4_TCD_CH_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_SBR_ATTR_SHIFT)) & EDMA4_TCD_CH_SBR_ATTR_MASK) 260 /*! @} */ 261 262 /*! @name CH_PRI - Channel Priority Register */ 263 /*! @{ */ 264 265 #define EDMA4_TCD_CH_PRI_APL_MASK (0x7U) 266 #define EDMA4_TCD_CH_PRI_APL_SHIFT (0U) 267 #define EDMA4_TCD_CH_PRI_APL_WIDTH (3U) 268 #define EDMA4_TCD_CH_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_PRI_APL_SHIFT)) & EDMA4_TCD_CH_PRI_APL_MASK) 269 270 #define EDMA4_TCD_CH_PRI_DPA_MASK (0x40000000U) 271 #define EDMA4_TCD_CH_PRI_DPA_SHIFT (30U) 272 #define EDMA4_TCD_CH_PRI_DPA_WIDTH (1U) 273 #define EDMA4_TCD_CH_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_PRI_DPA_SHIFT)) & EDMA4_TCD_CH_PRI_DPA_MASK) 274 275 #define EDMA4_TCD_CH_PRI_ECP_MASK (0x80000000U) 276 #define EDMA4_TCD_CH_PRI_ECP_SHIFT (31U) 277 #define EDMA4_TCD_CH_PRI_ECP_WIDTH (1U) 278 #define EDMA4_TCD_CH_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_CH_PRI_ECP_SHIFT)) & EDMA4_TCD_CH_PRI_ECP_MASK) 279 /*! @} */ 280 281 /*! @name CH_MATTR - Memory Attributes Register */ 282 /*! @{ */ 283 284 #define EDMA4_TCD_CH_MATTR_RCACHE_MASK (0xFU) 285 #define EDMA4_TCD_CH_MATTR_RCACHE_SHIFT (0U) 286 #define EDMA4_TCD_CH_MATTR_RCACHE_WIDTH (4U) 287 #define EDMA4_TCD_CH_MATTR_RCACHE(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_CH_MATTR_RCACHE_SHIFT)) & EDMA4_TCD_CH_MATTR_RCACHE_MASK) 288 289 #define EDMA4_TCD_CH_MATTR_WCACHE_MASK (0xF0U) 290 #define EDMA4_TCD_CH_MATTR_WCACHE_SHIFT (4U) 291 #define EDMA4_TCD_CH_MATTR_WCACHE_WIDTH (4U) 292 #define EDMA4_TCD_CH_MATTR_WCACHE(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_CH_MATTR_WCACHE_SHIFT)) & EDMA4_TCD_CH_MATTR_WCACHE_MASK) 293 /*! @} */ 294 295 /*! @name SADDR - TCD Source Address Register */ 296 /*! @{ */ 297 298 #define EDMA4_TCD_SADDR_SADDR_MASK (0xFFFFFFFFU) 299 #define EDMA4_TCD_SADDR_SADDR_SHIFT (0U) 300 #define EDMA4_TCD_SADDR_SADDR_WIDTH (32U) 301 #define EDMA4_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_SADDR_SADDR_SHIFT)) & EDMA4_TCD_SADDR_SADDR_MASK) 302 /*! @} */ 303 304 /*! @name SOFF - TCD Signed Source Address Offset Register */ 305 /*! @{ */ 306 307 #define EDMA4_TCD_SOFF_SOFF_MASK (0xFFFFU) 308 #define EDMA4_TCD_SOFF_SOFF_SHIFT (0U) 309 #define EDMA4_TCD_SOFF_SOFF_WIDTH (16U) 310 #define EDMA4_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_SOFF_SOFF_SHIFT)) & EDMA4_TCD_SOFF_SOFF_MASK) 311 /*! @} */ 312 313 /*! @name ATTR - TCD Transfer Attributes Register */ 314 /*! @{ */ 315 316 #define EDMA4_TCD_ATTR_DSIZE_MASK (0x7U) 317 #define EDMA4_TCD_ATTR_DSIZE_SHIFT (0U) 318 #define EDMA4_TCD_ATTR_DSIZE_WIDTH (3U) 319 #define EDMA4_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_ATTR_DSIZE_SHIFT)) & EDMA4_TCD_ATTR_DSIZE_MASK) 320 321 #define EDMA4_TCD_ATTR_DMOD_MASK (0xF8U) 322 #define EDMA4_TCD_ATTR_DMOD_SHIFT (3U) 323 #define EDMA4_TCD_ATTR_DMOD_WIDTH (5U) 324 #define EDMA4_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_ATTR_DMOD_SHIFT)) & EDMA4_TCD_ATTR_DMOD_MASK) 325 326 #define EDMA4_TCD_ATTR_SSIZE_MASK (0x700U) 327 #define EDMA4_TCD_ATTR_SSIZE_SHIFT (8U) 328 #define EDMA4_TCD_ATTR_SSIZE_WIDTH (3U) 329 #define EDMA4_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_ATTR_SSIZE_SHIFT)) & EDMA4_TCD_ATTR_SSIZE_MASK) 330 331 #define EDMA4_TCD_ATTR_SMOD_MASK (0xF800U) 332 #define EDMA4_TCD_ATTR_SMOD_SHIFT (11U) 333 #define EDMA4_TCD_ATTR_SMOD_WIDTH (5U) 334 #define EDMA4_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_ATTR_SMOD_SHIFT)) & EDMA4_TCD_ATTR_SMOD_MASK) 335 /*! @} */ 336 337 /*! @name NBYTES_MLOFFNO - TCD Transfer Size without Minor Loop Offsets Register */ 338 /*! @{ */ 339 340 #define EDMA4_TCD_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 341 #define EDMA4_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 342 #define EDMA4_TCD_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 343 #define EDMA4_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & EDMA4_TCD_NBYTES_MLOFFNO_NBYTES_MASK) 344 345 #define EDMA4_TCD_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 346 #define EDMA4_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 347 #define EDMA4_TCD_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 348 #define EDMA4_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & EDMA4_TCD_NBYTES_MLOFFNO_DMLOE_MASK) 349 350 #define EDMA4_TCD_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 351 #define EDMA4_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 352 #define EDMA4_TCD_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 353 #define EDMA4_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & EDMA4_TCD_NBYTES_MLOFFNO_SMLOE_MASK) 354 /*! @} */ 355 356 /*! @name NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets Register */ 357 /*! @{ */ 358 359 #define EDMA4_TCD_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 360 #define EDMA4_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 361 #define EDMA4_TCD_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 362 #define EDMA4_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & EDMA4_TCD_NBYTES_MLOFFYES_NBYTES_MASK) 363 364 #define EDMA4_TCD_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 365 #define EDMA4_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 366 #define EDMA4_TCD_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 367 #define EDMA4_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & EDMA4_TCD_NBYTES_MLOFFYES_MLOFF_MASK) 368 369 #define EDMA4_TCD_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 370 #define EDMA4_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 371 #define EDMA4_TCD_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 372 #define EDMA4_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & EDMA4_TCD_NBYTES_MLOFFYES_DMLOE_MASK) 373 374 #define EDMA4_TCD_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 375 #define EDMA4_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 376 #define EDMA4_TCD_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 377 #define EDMA4_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & EDMA4_TCD_NBYTES_MLOFFYES_SMLOE_MASK) 378 /*! @} */ 379 380 /*! @name SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address Register */ 381 /*! @{ */ 382 383 #define EDMA4_TCD_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 384 #define EDMA4_TCD_SLAST_SDA_SLAST_SDA_SHIFT (0U) 385 #define EDMA4_TCD_SLAST_SDA_SLAST_SDA_WIDTH (32U) 386 #define EDMA4_TCD_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & EDMA4_TCD_SLAST_SDA_SLAST_SDA_MASK) 387 /*! @} */ 388 389 /*! @name DADDR - TCD Destination Address Register */ 390 /*! @{ */ 391 392 #define EDMA4_TCD_DADDR_DADDR_MASK (0xFFFFFFFFU) 393 #define EDMA4_TCD_DADDR_DADDR_SHIFT (0U) 394 #define EDMA4_TCD_DADDR_DADDR_WIDTH (32U) 395 #define EDMA4_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_DADDR_DADDR_SHIFT)) & EDMA4_TCD_DADDR_DADDR_MASK) 396 /*! @} */ 397 398 /*! @name DOFF - TCD Signed Destination Address Offset Register */ 399 /*! @{ */ 400 401 #define EDMA4_TCD_DOFF_DOFF_MASK (0xFFFFU) 402 #define EDMA4_TCD_DOFF_DOFF_SHIFT (0U) 403 #define EDMA4_TCD_DOFF_DOFF_WIDTH (16U) 404 #define EDMA4_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_DOFF_DOFF_SHIFT)) & EDMA4_TCD_DOFF_DOFF_MASK) 405 /*! @} */ 406 407 /*! @name CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) Register */ 408 /*! @{ */ 409 410 #define EDMA4_TCD_CITER_ELINKNO_CITER_MASK (0x7FFFU) 411 #define EDMA4_TCD_CITER_ELINKNO_CITER_SHIFT (0U) 412 #define EDMA4_TCD_CITER_ELINKNO_CITER_WIDTH (15U) 413 #define EDMA4_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_CITER_ELINKNO_CITER_SHIFT)) & EDMA4_TCD_CITER_ELINKNO_CITER_MASK) 414 415 #define EDMA4_TCD_CITER_ELINKNO_ELINK_MASK (0x8000U) 416 #define EDMA4_TCD_CITER_ELINKNO_ELINK_SHIFT (15U) 417 #define EDMA4_TCD_CITER_ELINKNO_ELINK_WIDTH (1U) 418 #define EDMA4_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_CITER_ELINKNO_ELINK_SHIFT)) & EDMA4_TCD_CITER_ELINKNO_ELINK_MASK) 419 /*! @} */ 420 421 /*! @name CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) Register */ 422 /*! @{ */ 423 424 #define EDMA4_TCD_CITER_ELINKYES_CITER_MASK (0x1FFU) 425 #define EDMA4_TCD_CITER_ELINKYES_CITER_SHIFT (0U) 426 #define EDMA4_TCD_CITER_ELINKYES_CITER_WIDTH (9U) 427 #define EDMA4_TCD_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_CITER_ELINKYES_CITER_SHIFT)) & EDMA4_TCD_CITER_ELINKYES_CITER_MASK) 428 429 #define EDMA4_TCD_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 430 #define EDMA4_TCD_CITER_ELINKYES_LINKCH_SHIFT (9U) 431 #define EDMA4_TCD_CITER_ELINKYES_LINKCH_WIDTH (5U) 432 #define EDMA4_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & EDMA4_TCD_CITER_ELINKYES_LINKCH_MASK) 433 434 #define EDMA4_TCD_CITER_ELINKYES_ELINK_MASK (0x8000U) 435 #define EDMA4_TCD_CITER_ELINKYES_ELINK_SHIFT (15U) 436 #define EDMA4_TCD_CITER_ELINKYES_ELINK_WIDTH (1U) 437 #define EDMA4_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_CITER_ELINKYES_ELINK_SHIFT)) & EDMA4_TCD_CITER_ELINKYES_ELINK_MASK) 438 /*! @} */ 439 440 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address Register */ 441 /*! @{ */ 442 443 #define EDMA4_TCD_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 444 #define EDMA4_TCD_DLAST_SGA_DLAST_SGA_SHIFT (0U) 445 #define EDMA4_TCD_DLAST_SGA_DLAST_SGA_WIDTH (32U) 446 #define EDMA4_TCD_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << EDMA4_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & EDMA4_TCD_DLAST_SGA_DLAST_SGA_MASK) 447 /*! @} */ 448 449 /*! @name CSR - TCD Control and Status Register */ 450 /*! @{ */ 451 452 #define EDMA4_TCD_CSR_START_MASK (0x1U) 453 #define EDMA4_TCD_CSR_START_SHIFT (0U) 454 #define EDMA4_TCD_CSR_START_WIDTH (1U) 455 #define EDMA4_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_CSR_START_SHIFT)) & EDMA4_TCD_CSR_START_MASK) 456 457 #define EDMA4_TCD_CSR_INTMAJOR_MASK (0x2U) 458 #define EDMA4_TCD_CSR_INTMAJOR_SHIFT (1U) 459 #define EDMA4_TCD_CSR_INTMAJOR_WIDTH (1U) 460 #define EDMA4_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_CSR_INTMAJOR_SHIFT)) & EDMA4_TCD_CSR_INTMAJOR_MASK) 461 462 #define EDMA4_TCD_CSR_INTHALF_MASK (0x4U) 463 #define EDMA4_TCD_CSR_INTHALF_SHIFT (2U) 464 #define EDMA4_TCD_CSR_INTHALF_WIDTH (1U) 465 #define EDMA4_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_CSR_INTHALF_SHIFT)) & EDMA4_TCD_CSR_INTHALF_MASK) 466 467 #define EDMA4_TCD_CSR_DREQ_MASK (0x8U) 468 #define EDMA4_TCD_CSR_DREQ_SHIFT (3U) 469 #define EDMA4_TCD_CSR_DREQ_WIDTH (1U) 470 #define EDMA4_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_CSR_DREQ_SHIFT)) & EDMA4_TCD_CSR_DREQ_MASK) 471 472 #define EDMA4_TCD_CSR_ESG_MASK (0x10U) 473 #define EDMA4_TCD_CSR_ESG_SHIFT (4U) 474 #define EDMA4_TCD_CSR_ESG_WIDTH (1U) 475 #define EDMA4_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_CSR_ESG_SHIFT)) & EDMA4_TCD_CSR_ESG_MASK) 476 477 #define EDMA4_TCD_CSR_MAJORELINK_MASK (0x20U) 478 #define EDMA4_TCD_CSR_MAJORELINK_SHIFT (5U) 479 #define EDMA4_TCD_CSR_MAJORELINK_WIDTH (1U) 480 #define EDMA4_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_CSR_MAJORELINK_SHIFT)) & EDMA4_TCD_CSR_MAJORELINK_MASK) 481 482 #define EDMA4_TCD_CSR_ESDA_MASK (0x80U) 483 #define EDMA4_TCD_CSR_ESDA_SHIFT (7U) 484 #define EDMA4_TCD_CSR_ESDA_WIDTH (1U) 485 #define EDMA4_TCD_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_CSR_ESDA_SHIFT)) & EDMA4_TCD_CSR_ESDA_MASK) 486 487 #define EDMA4_TCD_CSR_MAJORLINKCH_MASK (0x1F00U) 488 #define EDMA4_TCD_CSR_MAJORLINKCH_SHIFT (8U) 489 #define EDMA4_TCD_CSR_MAJORLINKCH_WIDTH (5U) 490 #define EDMA4_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_CSR_MAJORLINKCH_SHIFT)) & EDMA4_TCD_CSR_MAJORLINKCH_MASK) 491 492 #define EDMA4_TCD_CSR_TMC_MASK (0xC000U) 493 #define EDMA4_TCD_CSR_TMC_SHIFT (14U) 494 #define EDMA4_TCD_CSR_TMC_WIDTH (2U) 495 #define EDMA4_TCD_CSR_TMC(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_CSR_TMC_SHIFT)) & EDMA4_TCD_CSR_TMC_MASK) 496 /*! @} */ 497 498 /*! @name BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) Register */ 499 /*! @{ */ 500 501 #define EDMA4_TCD_BITER_ELINKNO_BITER_MASK (0x7FFFU) 502 #define EDMA4_TCD_BITER_ELINKNO_BITER_SHIFT (0U) 503 #define EDMA4_TCD_BITER_ELINKNO_BITER_WIDTH (15U) 504 #define EDMA4_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_BITER_ELINKNO_BITER_SHIFT)) & EDMA4_TCD_BITER_ELINKNO_BITER_MASK) 505 506 #define EDMA4_TCD_BITER_ELINKNO_ELINK_MASK (0x8000U) 507 #define EDMA4_TCD_BITER_ELINKNO_ELINK_SHIFT (15U) 508 #define EDMA4_TCD_BITER_ELINKNO_ELINK_WIDTH (1U) 509 #define EDMA4_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_BITER_ELINKNO_ELINK_SHIFT)) & EDMA4_TCD_BITER_ELINKNO_ELINK_MASK) 510 /*! @} */ 511 512 /*! @name BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) Register */ 513 /*! @{ */ 514 515 #define EDMA4_TCD_BITER_ELINKYES_BITER_MASK (0x1FFU) 516 #define EDMA4_TCD_BITER_ELINKYES_BITER_SHIFT (0U) 517 #define EDMA4_TCD_BITER_ELINKYES_BITER_WIDTH (9U) 518 #define EDMA4_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_BITER_ELINKYES_BITER_SHIFT)) & EDMA4_TCD_BITER_ELINKYES_BITER_MASK) 519 520 #define EDMA4_TCD_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 521 #define EDMA4_TCD_BITER_ELINKYES_LINKCH_SHIFT (9U) 522 #define EDMA4_TCD_BITER_ELINKYES_LINKCH_WIDTH (5U) 523 #define EDMA4_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & EDMA4_TCD_BITER_ELINKYES_LINKCH_MASK) 524 525 #define EDMA4_TCD_BITER_ELINKYES_ELINK_MASK (0x8000U) 526 #define EDMA4_TCD_BITER_ELINKYES_ELINK_SHIFT (15U) 527 #define EDMA4_TCD_BITER_ELINKYES_ELINK_WIDTH (1U) 528 #define EDMA4_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << EDMA4_TCD_BITER_ELINKYES_ELINK_SHIFT)) & EDMA4_TCD_BITER_ELINKYES_ELINK_MASK) 529 /*! @} */ 530 531 /*! 532 * @} 533 */ /* end of group EDMA4_TCD_Register_Masks */ 534 535 /*! 536 * @} 537 */ /* end of group EDMA4_TCD_Peripheral_Access_Layer */ 538 539 #endif /* #if !defined(S32Z2_EDMA4_TCD_H_) */ 540
