Searched refs:EDMA4PCTL (Results 1 – 2 of 2) sorted by relevance
75 __IO uint32_t EDMA4PCTL; /**< eDMA_4 Clock Control Enable, offset: 0x8 */ member
2411 …Frequency &= Clock_Ip_u64EnableGate[((IP_GPR4_PCTL->EDMA4PCTL & GPR4_PCTL_EDMA4PCTL_PCTL_1_MASK) >… in Clock_Ip_Get_DMACRC4_CLK_Frequency()2453 …divider value */ Frequency &= Clock_Ip_u64EnableGate[((IP_GPR4_PCTL->EDMA4PCTL & GPR4_PCTL_EDMA… in Clock_Ip_Get_DMAMUX4_CLK_Frequency()2595 …Frequency &= Clock_Ip_u64EnableGate[((IP_GPR4_PCTL->EDMA4PCTL & GPR4_PCTL_EDMA4PCTL_PCTL_0_MASK) >… in Clock_Ip_Get_EDMA4_CLK_Frequency()3799 …Frequency &= Clock_Ip_u64EnableGate[((IP_GPR4_PCTL->EDMA4PCTL & GPR4_PCTL_EDMA4PCTL_PCTL_3_MASK) >… in Clock_Ip_Get_PIT4_CLK_Frequency()
