| /hal_nxp-latest/mcux/mcux-sdk/drivers/esai/ |
| D | fsl_esai.h | 330 base->ECR |= ESAI_ECR_ESAIEN_MASK; in ESAI_Enable()
334 base->ECR &= ~ESAI_ECR_ESAIEN_MASK; in ESAI_Enable()
348 base->ECR |= ESAI_ECR_ERST_MASK; in ESAI_Reset()
349 base->ECR &= ~ESAI_ECR_ERST_MASK; in ESAI_Reset()
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| D | fsl_esai.c | 403 base->ECR |= ESAI_ECR_ERI_MASK; in ESAI_Init()
407 base->ECR &= 0xFFF0FFFFU; in ESAI_Init()
408 base->ECR |= in ESAI_Init()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/enet/ |
| D | fsl_enet.h | 920 base->ECR |= ENET_ECR_RESET_MASK; in ENET_Reset()
1140 uint32_t ecrReg = base->ECR; in ENET_SetRGMIIClockDelay()
1165 base->ECR = ecrReg; in ENET_SetRGMIIClockDelay()
1274 base->ECR |= ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK; in ENET_EnableSleepMode()
1278 base->ECR &= ~(ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK); in ENET_EnableSleepMode()
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| D | fsl_enet.c | 369 base->ECR &= ~ENET_ECR_ETHEREN_MASK; in ENET_Down()
549 uint32_t ecr = base->ECR; in ENET_SetMacController()
790 base->ECR = ecr; in ENET_SetMacController()
1109 uint32_t ecr = base->ECR; in ENET_SetMII()
1121 base->ECR = ecr; in ENET_SetMII()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/smartcard/ |
| D | fsl_smartcard_usim.c | 281 base->ECR = (base->ECR & ~(USIM_ECR_T0ERR_TL_MASK | USIM_ECR_PE_TL_MASK)) | in SMARTCARD_USIM_SetTransferType()
307 base->ECR = (base->ECR & ~(USIM_ECR_T0ERR_TL_MASK | USIM_ECR_PE_TL_MASK)) | in SMARTCARD_USIM_SetTransferType()
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| /hal_nxp-latest/mcux/mcux-sdk/cmsis_drivers/enet/ |
| D | fsl_enet_cmsis.c | 162 uint32_t ecr = enet->resource->base->ECR; in ENET_CommonControl()
257 enet->resource->base->ECR = ecr; in ENET_CommonControl()
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| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_DIPORTSD.h | 74 __IO uint32_t ECR; /**< Error and Control Register, offset: 0x100 */ member
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| D | S32Z2_FLEXCAN.h | 85 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/flexcan/ |
| D | fsl_flexcan.h | 1525 *txErrBuf = (uint8_t)((base->ECR & CAN_ECR_TXERRCNT_MASK) >> CAN_ECR_TXERRCNT_SHIFT); in FLEXCAN_GetBusErrCount()
1530 *rxErrBuf = (uint8_t)((base->ECR & CAN_ECR_RXERRCNT_MASK) >> CAN_ECR_RXERRCNT_SHIFT); in FLEXCAN_GetBusErrCount()
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| /hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/ |
| D | S32K148_FLEXCAN.h | 85 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ member
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| D | S32K118_FLEXCAN.h | 85 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ member
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| D | S32K116_FLEXCAN.h | 85 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ member
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| D | S32K142W_FLEXCAN.h | 85 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ member
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| D | S32K146_FLEXCAN.h | 85 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ member
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| D | S32K142_FLEXCAN.h | 85 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ member
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| D | S32K144_FLEXCAN.h | 85 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ member
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| D | S32K144W_FLEXCAN.h | 85 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ member
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| D | S32K148_ENET.h | 83 __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ member
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| /hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/ |
| D | S32K344_FLEXCAN.h | 85 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ member
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| /hal_nxp-latest/s32/mcux/devices/S32K344/ |
| D | S32K344_device.h | 28 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ member
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| /hal_nxp-latest/s32/mcux/devices/S32Z270/ |
| D | S32Z270_device.h | 28 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ member
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| /hal_nxp-latest/imx/devices/MCIMX6X/ |
| D | MCIMX6X_M4.h | 3399 …__IO uint32_t ECR; /**< Error Counter Register, offset: 0x1C */ member
3440 #define CAN_ECR_REG(base) ((base)->ECR)
8452 …__IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x2… member
8594 #define ENET_ECR_REG(base) ((base)->ECR)
9877 __IO uint32_t ECR; /**< ESAI Control Register, offset: 0x8 */ member
9916 #define ESAI_ECR_REG(base) ((base)->ECR)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MK64F12/ |
| D | MK64F12.h | 4667 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ member
9718 __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MK63F12/ |
| D | MK63F12.h | 4654 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ member
9705 __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKV11Z7/ |
| D | MKV11Z7.h | 746 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ member
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