| /hal_nxp-latest/mcux/mcux-sdk/devices/MK66F18/ |
| D | system_MK66F18.c | 110 uint16_t Divider; in SystemCoreClockUpdate() local
135 Divider = 1536U; in SystemCoreClockUpdate()
138 Divider = 1280U; in SystemCoreClockUpdate()
141 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
145 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
147 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
184 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U); in SystemCoreClockUpdate()
185 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
186 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U); in SystemCoreClockUpdate()
187 MCGOUTClock *= Divider; /* Calculate the VCO output clock */ in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MK65F18/ |
| D | system_MK65F18.c | 110 uint16_t Divider; in SystemCoreClockUpdate() local
135 Divider = 1536U; in SystemCoreClockUpdate()
138 Divider = 1280U; in SystemCoreClockUpdate()
141 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
145 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
147 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
184 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U); in SystemCoreClockUpdate()
185 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
186 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U); in SystemCoreClockUpdate()
187 MCGOUTClock *= Divider; /* Calculate the VCO output clock */ in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MK26F18/ |
| D | system_MK26F18.c | 97 uint16_t Divider; in SystemCoreClockUpdate() local
122 Divider = 1536U; in SystemCoreClockUpdate()
125 Divider = 1280U; in SystemCoreClockUpdate()
128 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
132 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
134 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
171 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U); in SystemCoreClockUpdate()
172 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
173 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U); in SystemCoreClockUpdate()
174 MCGOUTClock *= Divider; /* Calculate the VCO output clock */ in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MKM14ZA5/ |
| D | system_MKM14ZA5.c | 88 uint16_t Divider; in SystemCoreClockUpdate() local
104 Divider = 1536U; in SystemCoreClockUpdate()
107 Divider = 1280U; in SystemCoreClockUpdate()
110 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
114 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
116 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
169 Divider = 1536U; in SystemCoreClockUpdate()
172 Divider = 1280U; in SystemCoreClockUpdate()
175 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
179 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MKM33ZA5/ |
| D | system_MKM33ZA5.c | 90 uint16_t Divider; in SystemCoreClockUpdate() local
106 Divider = 1536U; in SystemCoreClockUpdate()
109 Divider = 1280U; in SystemCoreClockUpdate()
112 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
116 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
118 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
171 Divider = 1536U; in SystemCoreClockUpdate()
174 Divider = 1280U; in SystemCoreClockUpdate()
177 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
181 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MKM34ZA5/ |
| D | system_MKM34ZA5.c | 86 uint16_t Divider; in SystemCoreClockUpdate() local
102 Divider = 1536U; in SystemCoreClockUpdate()
105 Divider = 1280U; in SystemCoreClockUpdate()
108 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
112 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
114 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
167 Divider = 1536U; in SystemCoreClockUpdate()
170 Divider = 1280U; in SystemCoreClockUpdate()
173 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
177 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MKM35Z7/ |
| D | system_MKM35Z7.c | 96 uint16_t Divider; in SystemCoreClockUpdate() local
112 Divider = 1536U; in SystemCoreClockUpdate()
115 Divider = 1280U; in SystemCoreClockUpdate()
118 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
122 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
124 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
177 Divider = 1536U; in SystemCoreClockUpdate()
180 Divider = 1280U; in SystemCoreClockUpdate()
183 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
187 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MKM34Z7/ |
| D | system_MKM34Z7.c | 89 uint16_t Divider; in SystemCoreClockUpdate() local
113 Divider = 1536U; in SystemCoreClockUpdate()
116 Divider = 1280U; in SystemCoreClockUpdate()
119 … Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
125 … Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
127 … MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
194 Divider = 1536U; in SystemCoreClockUpdate()
197 Divider = 1280U; in SystemCoreClockUpdate()
200 … Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
206 … Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MKL25Z4/ |
| D | system_MKL25Z4.c | 135 uint16_t Divider; in SystemCoreClockUpdate() local
147 Divider = 1536U; in SystemCoreClockUpdate()
150 Divider = 1280U; in SystemCoreClockUpdate()
153 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
157 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
159 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
194 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
195 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
196 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
197 MCGOUTClock *= Divider; /* Calculate the MCG output clock */ in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MK22F12/ |
| D | system_MK22F12.c | 127 uint16_t Divider; in SystemCoreClockUpdate() local
145 Divider = 1536U; in SystemCoreClockUpdate()
148 Divider = 1280U; in SystemCoreClockUpdate()
151 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
155 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
157 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
193 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
194 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
195 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
196 MCGOUTClock *= Divider; /* Calculate the MCG output clock */ in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F51212/ |
| D | system_MKV31F51212.c | 110 uint16_t Divider; in SystemCoreClockUpdate() local
132 Divider = 1536U; in SystemCoreClockUpdate()
135 Divider = 1280U; in SystemCoreClockUpdate()
138 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
142 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
144 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
180 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
181 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
182 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
183 MCGOUTClock *= Divider; /* Calculate the MCG output clock */ in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F25612/ |
| D | system_MKV31F25612.c | 110 uint16_t Divider; in SystemCoreClockUpdate() local
132 Divider = 1536U; in SystemCoreClockUpdate()
135 Divider = 1280U; in SystemCoreClockUpdate()
138 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
142 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
144 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
180 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
181 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
182 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
183 MCGOUTClock *= Divider; /* Calculate the MCG output clock */ in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MK22F25612/ |
| D | system_MK22F25612.c | 115 uint16_t Divider; in SystemCoreClockUpdate() local
140 Divider = 1536U; in SystemCoreClockUpdate()
143 Divider = 1280U; in SystemCoreClockUpdate()
146 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
150 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
152 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
188 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
189 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
190 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
191 MCGOUTClock *= Divider; /* Calculate the MCG output clock */ in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MK64F12/ |
| D | system_MK64F12.c | 129 uint16_t Divider; in SystemCoreClockUpdate() local
154 Divider = 1536U; in SystemCoreClockUpdate()
157 Divider = 1280U; in SystemCoreClockUpdate()
160 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
164 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
166 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
202 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
203 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
204 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
205 MCGOUTClock *= Divider; /* Calculate the MCG output clock */ in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MK24F12/ |
| D | system_MK24F12.c | 121 uint16_t Divider; in SystemCoreClockUpdate() local
146 Divider = 1536U; in SystemCoreClockUpdate()
149 Divider = 1280U; in SystemCoreClockUpdate()
152 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
156 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
158 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
194 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
195 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
196 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
197 MCGOUTClock *= Divider; /* Calculate the MCG output clock */ in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MK22F51212/ |
| D | system_MK22F51212.c | 125 uint16_t Divider; in SystemCoreClockUpdate() local
150 Divider = 1536U; in SystemCoreClockUpdate()
153 Divider = 1280U; in SystemCoreClockUpdate()
156 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
160 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
162 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
198 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
199 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
200 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
201 MCGOUTClock *= Divider; /* Calculate the MCG output clock */ in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MK63F12/ |
| D | system_MK63F12.c | 116 uint16_t Divider; in SystemCoreClockUpdate() local
141 Divider = 1536U; in SystemCoreClockUpdate()
144 Divider = 1280U; in SystemCoreClockUpdate()
147 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
151 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
153 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
189 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
190 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
191 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
192 MCGOUTClock *= Divider; /* Calculate the MCG output clock */ in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/ |
| D | system_MK27FA15.c | 97 uint16_t Divider; in SystemCoreClockUpdate() local
122 Divider = 1536U; in SystemCoreClockUpdate()
125 Divider = 1280U; in SystemCoreClockUpdate()
128 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
132 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
134 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
170 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U); in SystemCoreClockUpdate()
171 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
172 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U); in SystemCoreClockUpdate()
173 MCGOUTClock *= Divider; /* Calculate the VCO output clock */ in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/ |
| D | system_MK28FA15.c | 99 uint16_t Divider; in SystemCoreClockUpdate() local
124 Divider = 1536U; in SystemCoreClockUpdate()
127 Divider = 1280U; in SystemCoreClockUpdate()
130 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
134 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
136 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
172 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U); in SystemCoreClockUpdate()
173 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
174 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U); in SystemCoreClockUpdate()
175 MCGOUTClock *= Divider; /* Calculate the VCO output clock */ in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/ |
| D | system_MK82F25615.c | 98 uint16_t Divider; in SystemCoreClockUpdate() local
123 Divider = 1536U; in SystemCoreClockUpdate()
126 Divider = 1280U; in SystemCoreClockUpdate()
129 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
133 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
135 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
171 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U); in SystemCoreClockUpdate()
172 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
173 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U); in SystemCoreClockUpdate()
174 MCGOUTClock *= Divider; /* Calculate the VCO output clock */ in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/ |
| D | system_MK80F25615.c | 104 uint16_t Divider; in SystemCoreClockUpdate() local
129 Divider = 1536U; in SystemCoreClockUpdate()
132 Divider = 1280U; in SystemCoreClockUpdate()
135 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
139 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
141 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
177 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U); in SystemCoreClockUpdate()
178 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
179 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U); in SystemCoreClockUpdate()
180 MCGOUTClock *= Divider; /* Calculate the VCO output clock */ in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MKW24D5/ |
| D | system_MKW24D5.c | 144 uint16_t Divider; in SystemCoreClockUpdate() local
160 Divider = 1536U; in SystemCoreClockUpdate()
163 Divider = 1280U; in SystemCoreClockUpdate()
166 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
170 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
172 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
207 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
208 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
209 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
210 MCGOUTClock *= Divider; /* Calculate the MCG output clock */ in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MKW22D5/ |
| D | system_MKW22D5.c | 144 uint16_t Divider; in SystemCoreClockUpdate() local
160 Divider = 1536U; in SystemCoreClockUpdate()
163 Divider = 1280U; in SystemCoreClockUpdate()
166 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
170 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
172 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
207 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
208 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
209 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
210 MCGOUTClock *= Divider; /* Calculate the MCG output clock */ in SystemCoreClockUpdate()
[all …]
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MKV58F24/ |
| D | system_MKV58F24.c | 112 uint16_t Divider; in SystemCoreClockUpdate() local
124 Divider = 1536; in SystemCoreClockUpdate()
127 Divider = 1280; in SystemCoreClockUpdate()
130 Divider = (uint16_t)(32U << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
134 Divider = (uint16_t)(1U << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
136 …MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FL… in SystemCoreClockUpdate()
172 Divider = (1U + (MCG->C5 & MCG_C5_PRDIV_MASK)); in SystemCoreClockUpdate()
173 …MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL refe… in SystemCoreClockUpdate()
174 Divider = ((MCG->C6 & MCG_C6_VDIV_MASK) + 16U); in SystemCoreClockUpdate()
175 …MCGOUTClock = ((MCGOUTClock * Divider) >> 1U); /* Calculate the MCG outp… in SystemCoreClockUpdate()
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MKV56F24/ |
| D | system_MKV56F24.c | 112 uint16_t Divider; in SystemCoreClockUpdate() local
124 Divider = 1536; in SystemCoreClockUpdate()
127 Divider = 1280; in SystemCoreClockUpdate()
130 Divider = (uint16_t)(32U << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
134 Divider = (uint16_t)(1U << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
136 …MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FL… in SystemCoreClockUpdate()
172 Divider = (1U + (MCG->C5 & MCG_C5_PRDIV_MASK)); in SystemCoreClockUpdate()
173 …MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL refe… in SystemCoreClockUpdate()
174 Divider = ((MCG->C6 & MCG_C6_VDIV_MASK) + 16U); in SystemCoreClockUpdate()
175 …MCGOUTClock = ((MCGOUTClock * Divider) >> 1U); /* Calculate the MCG outp… in SystemCoreClockUpdate()
|
