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Searched refs:DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR_MASK (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML6/
DMIMX8ML6_cm7.h26273 #define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR_MASK (0xFFFFU) macro
26278 …YA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML4/
DMIMX8ML4_cm7.h26273 #define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR_MASK (0xFFFFU) macro
26278 …YA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML3/
DMIMX8ML3_cm7.h26273 #define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR_MASK (0xFFFFU) macro
26278 …YA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML8/
DMIMX8ML8_dsp.h25321 #define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR_MASK (0xFFFFU) macro
25326 …YA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR…
DMIMX8ML8_cm7.h26273 #define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR_MASK (0xFFFFU) macro
26278 …YA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR…
DMIMX8ML8_ca53.h26300 #define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR_MASK (0xFFFFU) macro
26305 …YA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PHYUPD1FAILCTR…