1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2022 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #ifndef FSL_DSPI_H_
9 #define FSL_DSPI_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup dspi_driver
15 * @{
16 */
17
18 /**********************************************************************************************************************
19 * Definitions
20 *********************************************************************************************************************/
21
22 /*! @name Driver version */
23 /*! @{ */
24 /*! @brief DSPI driver version 2.2.5. */
25 #define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 6))
26 /*! @} */
27
28 #ifndef DSPI_DUMMY_DATA
29 /*! @brief DSPI dummy data if there is no Tx data.*/
30 #define DSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for Tx if there is no txData. */
31 #endif
32
33 /*! @brief Global variable for dummy data value setting. */
34 extern volatile uint8_t g_dspiDummyData[];
35
36 /*! @brief Status for the DSPI driver.*/
37 enum
38 {
39 kStatus_DSPI_Busy = MAKE_STATUS(kStatusGroup_DSPI, 0), /*!< DSPI transfer is busy.*/
40 kStatus_DSPI_Error = MAKE_STATUS(kStatusGroup_DSPI, 1), /*!< DSPI driver error. */
41 kStatus_DSPI_Idle = MAKE_STATUS(kStatusGroup_DSPI, 2), /*!< DSPI is idle.*/
42 kStatus_DSPI_OutOfRange = MAKE_STATUS(kStatusGroup_DSPI, 3) /*!< DSPI transfer out of range. */
43 };
44
45 /*! @brief DSPI status flags in SPIx_SR register.*/
46 enum _dspi_flags
47 {
48 kDSPI_TxCompleteFlag = (int)SPI_SR_TCF_MASK, /*!< Transfer Complete Flag. */
49 kDSPI_EndOfQueueFlag = SPI_SR_EOQF_MASK, /*!< End of Queue Flag.*/
50 #if !(defined(FSL_FEATURE_DSPI_HAS_NO_SR_TFUF_SUPPORT) && FSL_FEATURE_DSPI_HAS_NO_SR_TFUF_SUPPORT)
51 kDSPI_TxFifoUnderflowFlag = SPI_SR_TFUF_MASK, /*!< Transmit FIFO Underflow Flag.*/
52 #endif
53 kDSPI_TxFifoFillRequestFlag = SPI_SR_TFFF_MASK, /*!< Transmit FIFO Fill Flag.*/
54 kDSPI_RxFifoOverflowFlag = SPI_SR_RFOF_MASK, /*!< Receive FIFO Overflow Flag.*/
55 kDSPI_RxFifoDrainRequestFlag = SPI_SR_RFDF_MASK, /*!< Receive FIFO Drain Flag.*/
56 kDSPI_TxAndRxStatusFlag = SPI_SR_TXRXS_MASK, /*!< The module is in Stopped/Running state.*/
57 kDSPI_AllStatusFlag = (int)(SPI_SR_TCF_MASK | SPI_SR_EOQF_MASK |
58 #if !(defined(FSL_FEATURE_DSPI_HAS_NO_SR_TFUF_SUPPORT) && FSL_FEATURE_DSPI_HAS_NO_SR_TFUF_SUPPORT)
59 SPI_SR_TFUF_MASK |
60 #endif
61 SPI_SR_TFFF_MASK | SPI_SR_RFOF_MASK | SPI_SR_RFDF_MASK | SPI_SR_TXRXS_MASK) /*!< All statuses above.*/
62 };
63
64 /*! @brief DSPI interrupt source.*/
65 enum _dspi_interrupt_enable
66 {
67 kDSPI_TxCompleteInterruptEnable = (int)SPI_RSER_TCF_RE_MASK, /*!< TCF interrupt enable.*/
68 kDSPI_EndOfQueueInterruptEnable = SPI_RSER_EOQF_RE_MASK, /*!< EOQF interrupt enable.*/
69 #if !(defined(FSL_FEATURE_DSPI_HAS_NO_RSER_TFUF_RE_SUPPORT) && FSL_FEATURE_DSPI_HAS_NO_RSER_TFUF_RE_SUPPORT)
70 kDSPI_TxFifoUnderflowInterruptEnable = SPI_RSER_TFUF_RE_MASK, /*!< TFUF interrupt enable.*/
71 #endif
72 kDSPI_TxFifoFillRequestInterruptEnable = SPI_RSER_TFFF_RE_MASK, /*!< TFFF interrupt enable, DMA disable.*/
73 kDSPI_RxFifoOverflowInterruptEnable = SPI_RSER_RFOF_RE_MASK, /*!< RFOF interrupt enable.*/
74 kDSPI_RxFifoDrainRequestInterruptEnable = SPI_RSER_RFDF_RE_MASK, /*!< RFDF interrupt enable, DMA disable.*/
75 kDSPI_AllInterruptEnable = (int)(SPI_RSER_TCF_RE_MASK | SPI_RSER_EOQF_RE_MASK |
76 #if !(defined(FSL_FEATURE_DSPI_HAS_NO_RSER_TFUF_RE_SUPPORT) && FSL_FEATURE_DSPI_HAS_NO_RSER_TFUF_RE_SUPPORT)
77 SPI_RSER_TFUF_RE_MASK |
78 #endif
79 SPI_RSER_TFFF_RE_MASK | SPI_RSER_RFOF_RE_MASK | SPI_RSER_RFDF_RE_MASK)
80 /*!< All above interrupts enable.*/
81 };
82
83 /*! @brief DSPI DMA source.*/
84 enum _dspi_dma_enable
85 {
86 kDSPI_TxDmaEnable = (SPI_RSER_TFFF_RE_MASK | SPI_RSER_TFFF_DIRS_MASK), /*!< TFFF flag generates DMA requests.
87 No Tx interrupt request. */
88 kDSPI_RxDmaEnable = (SPI_RSER_RFDF_RE_MASK | SPI_RSER_RFDF_DIRS_MASK) /*!< RFDF flag generates DMA requests.
89 No Rx interrupt request. */
90 };
91
92 /*! @brief DSPI master or slave mode configuration.*/
93 typedef enum _dspi_master_slave_mode
94 {
95 kDSPI_Master = 1U, /*!< DSPI peripheral operates in master mode.*/
96 kDSPI_Slave = 0U /*!< DSPI peripheral operates in slave mode.*/
97 } dspi_master_slave_mode_t;
98
99 /*!
100 * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in the Modified Transfer Format. This field is
101 * valid only when the CPHA bit in the CTAR register is 0.
102 */
103 typedef enum _dspi_master_sample_point
104 {
105 kDSPI_SckToSin0Clock = 0U, /*!< 0 system clocks between SCK edge and SIN sample.*/
106 kDSPI_SckToSin1Clock = 1U, /*!< 1 system clock between SCK edge and SIN sample.*/
107 kDSPI_SckToSin2Clock = 2U /*!< 2 system clocks between SCK edge and SIN sample.*/
108 } dspi_master_sample_point_t;
109
110 /*! @brief DSPI Peripheral Chip Select (Pcs) configuration (which Pcs to configure).*/
111 typedef enum _dspi_which_pcs_config
112 {
113 kDSPI_Pcs0 = 1U << 0, /*!< Pcs[0] */
114 kDSPI_Pcs1 = 1U << 1, /*!< Pcs[1] */
115 kDSPI_Pcs2 = 1U << 2, /*!< Pcs[2] */
116 kDSPI_Pcs3 = 1U << 3, /*!< Pcs[3] */
117 kDSPI_Pcs4 = 1U << 4, /*!< Pcs[4] */
118 kDSPI_Pcs5 = 1U << 5 /*!< Pcs[5] */
119 } dspi_which_pcs_t;
120
121 /*! @brief DSPI Peripheral Chip Select (Pcs) Polarity configuration.*/
122 typedef enum _dspi_pcs_polarity_config
123 {
124 kDSPI_PcsActiveHigh = 0U, /*!< Pcs Active High (idles low). */
125 kDSPI_PcsActiveLow = 1U /*!< Pcs Active Low (idles high). */
126 } dspi_pcs_polarity_config_t;
127
128 /*! @brief DSPI Peripheral Chip Select (Pcs) Polarity.*/
129 enum _dspi_pcs_polarity
130 {
131 kDSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */
132 kDSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */
133 kDSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */
134 kDSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */
135 kDSPI_Pcs4ActiveLow = 1U << 4, /*!< Pcs4 Active Low (idles high). */
136 kDSPI_Pcs5ActiveLow = 1U << 5, /*!< Pcs5 Active Low (idles high). */
137 kDSPI_PcsAllActiveLow = 0xFFU /*!< Pcs0 to Pcs5 Active Low (idles high). */
138 };
139
140 /*! @brief DSPI clock polarity configuration for a given CTAR.*/
141 typedef enum _dspi_clock_polarity
142 {
143 kDSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high DSPI clock (idles low).*/
144 kDSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low DSPI clock (idles high).*/
145 } dspi_clock_polarity_t;
146
147 /*! @brief DSPI clock phase configuration for a given CTAR.*/
148 typedef enum _dspi_clock_phase
149 {
150 kDSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the
151 following edge.*/
152 kDSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the
153 following edge.*/
154 } dspi_clock_phase_t;
155
156 /*! @brief DSPI data shifter direction options for a given CTAR.*/
157 typedef enum _dspi_shift_direction
158 {
159 kDSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/
160 kDSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit.
161 Shifting out of LSB is not supported for slave */
162 } dspi_shift_direction_t;
163
164 /*! @brief DSPI delay type selection.*/
165 typedef enum _dspi_delay_type
166 {
167 kDSPI_PcsToSck = 1U, /*!< Pcs-to-SCK delay. */
168 kDSPI_LastSckToPcs, /*!< The last SCK edge to Pcs delay. */
169 kDSPI_BetweenTransfer /*!< Delay between transfers. */
170 } dspi_delay_type_t;
171
172 /*! @brief DSPI Clock and Transfer Attributes Register (CTAR) selection.*/
173 typedef enum _dspi_ctar_selection
174 {
175 kDSPI_Ctar0 = 0U, /*!< CTAR0 selection option for master or slave mode; note that CTAR0 and CTAR0_SLAVE are the
176 same register address. */
177 kDSPI_Ctar1 = 1U, /*!< CTAR1 selection option for master mode only. */
178 kDSPI_Ctar2 = 2U, /*!< CTAR2 selection option for master mode only; note that some devices do not support CTAR2. */
179 kDSPI_Ctar3 = 3U, /*!< CTAR3 selection option for master mode only; note that some devices do not support CTAR3. */
180 kDSPI_Ctar4 = 4U, /*!< CTAR4 selection option for master mode only; note that some devices do not support CTAR4. */
181 kDSPI_Ctar5 = 5U, /*!< CTAR5 selection option for master mode only; note that some devices do not support CTAR5. */
182 kDSPI_Ctar6 = 6U, /*!< CTAR6 selection option for master mode only; note that some devices do not support CTAR6. */
183 kDSPI_Ctar7 = 7U /*!< CTAR7 selection option for master mode only; note that some devices do not support CTAR7. */
184 } dspi_ctar_selection_t;
185
186 #define DSPI_MASTER_CTAR_SHIFT (0U) /*!< DSPI master CTAR shift macro; used internally. */
187 #define DSPI_MASTER_CTAR_MASK (0x0FU) /*!< DSPI master CTAR mask macro; used internally. */
188 #define DSPI_MASTER_PCS_SHIFT (4U) /*!< DSPI master PCS shift macro; used internally. */
189 #define DSPI_MASTER_PCS_MASK (0xF0U) /*!< DSPI master PCS mask macro; used internally. */
190 /*! @brief Use this enumeration for the DSPI master transfer configFlags. */
191 enum _dspi_transfer_config_flag_for_master
192 {
193 kDSPI_MasterCtar0 = 0U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR0 setting. */
194 kDSPI_MasterCtar1 = 1U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR1 setting. */
195 kDSPI_MasterCtar2 = 2U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR2 setting. */
196 kDSPI_MasterCtar3 = 3U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR3 setting. */
197 kDSPI_MasterCtar4 = 4U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR4 setting. */
198 kDSPI_MasterCtar5 = 5U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR5 setting. */
199 kDSPI_MasterCtar6 = 6U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR6 setting. */
200 kDSPI_MasterCtar7 = 7U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR7 setting. */
201
202 kDSPI_MasterPcs0 = 0U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS0 signal. */
203 kDSPI_MasterPcs1 = 1U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS1 signal. */
204 kDSPI_MasterPcs2 = 2U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS2 signal.*/
205 kDSPI_MasterPcs3 = 3U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS3 signal. */
206 kDSPI_MasterPcs4 = 4U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS4 signal. */
207 kDSPI_MasterPcs5 = 5U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS5 signal. */
208
209 kDSPI_MasterPcsContinuous = 1U << 20, /*!< Indicates whether the PCS signal is continuous. */
210 kDSPI_MasterActiveAfterTransfer = 1U << 21,
211 /*!< Indicates whether the PCS signal is active after the last frame transfer.*/
212 };
213
214 #if !(defined(FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT) && FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT)
215 #define DSPI_SLAVE_CTAR_SHIFT (0U) /*!< DSPI slave CTAR shift macro; used internally. */
216 #define DSPI_SLAVE_CTAR_MASK (0x07U) /*!< DSPI slave CTAR mask macro; used internally. */
217 #endif
218 #if !(defined(FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT) && FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT)
219 /*! @brief Use this enumeration for the DSPI slave transfer configFlags. */
220 enum _dspi_transfer_config_flag_for_slave
221 {
222 kDSPI_SlaveCtar0 = 0U << DSPI_SLAVE_CTAR_SHIFT, /*!< DSPI slave transfer use CTAR0 setting.
223 DSPI slave can only use PCS0. */
224 };
225 #endif
226
227 /*! @brief DSPI transfer state, which is used for DSPI transactional API state machine. */
228 enum _dspi_transfer_state
229 {
230 kDSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */
231 kDSPI_Busy, /*!< Transfer queue is not finished. */
232 kDSPI_Error /*!< Transfer error. */
233 };
234
235 /*! @brief DSPI master command date configuration used for the SPIx_PUSHR.*/
236 typedef struct _dspi_command_data_config
237 {
238 bool isPcsContinuous; /*!< Option to enable the continuous assertion of the chip select between transfers.*/
239 uint8_t whichCtar; /*!< The desired Clock and Transfer Attributes
240 Register (CTAR) to use for CTAS.*/
241 uint8_t whichPcs; /*!< The desired PCS signal to use for the data transfer.*/
242 bool isEndOfQueue; /*!< Signals that the current transfer is the last in the queue.*/
243 bool clearTransferCount; /*!< Clears the SPI Transfer Counter (SPI_TCNT) before transmission starts.*/
244 } dspi_command_data_config_t;
245
246 /*! @brief DSPI master ctar configuration structure.*/
247 typedef struct _dspi_master_ctar_config
248 {
249 uint32_t baudRate; /*!< Baud Rate for DSPI. */
250 uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16.*/
251 dspi_clock_polarity_t cpol; /*!< Clock polarity. */
252 dspi_clock_phase_t cpha; /*!< Clock phase. */
253 dspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */
254
255 uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds; setting to 0 sets the minimum
256 delay. It also sets the boundary value if out of range.*/
257 uint32_t lastSckToPcsDelayInNanoSec; /*!< The last SCK to PCS delay time in nanoseconds; setting to 0 sets the
258 minimum delay. It also sets the boundary value if out of range.*/
259
260 uint32_t betweenTransferDelayInNanoSec;
261 /*!< After the SCK delay time in nanoseconds; setting to 0 sets the minimum
262 delay. It also sets the boundary value if out of range.*/
263 } dspi_master_ctar_config_t;
264
265 /*! @brief DSPI master configuration structure.*/
266 typedef struct _dspi_master_config
267 {
268 dspi_ctar_selection_t whichCtar; /*!< The desired CTAR to use. */
269 dspi_master_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */
270
271 dspi_which_pcs_t whichPcs; /*!< The desired Peripheral Chip Select (pcs). */
272 dspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< The desired PCS active high or low. */
273
274 bool enableContinuousSCK; /*!< CONT_SCKE, continuous SCK enable. Note that the continuous SCK is only
275 supported for CPHA = 1.*/
276 bool enableRxFifoOverWrite; /*!< ROOE, receive FIFO overflow overwrite enable. If ROOE = 0, the incoming
277 data is ignored and the data from the transfer that generated the overflow
278 is also ignored. If ROOE = 1, the incoming data is shifted to the
279 shift register. */
280
281 bool enableModifiedTimingFormat; /*!< Enables a modified transfer format to be used if true.*/
282 dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in the Modified Transfer
283 Format. It's valid only when CPHA=0. */
284 } dspi_master_config_t;
285
286 #if !(defined(FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT) && FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT)
287 /*! @brief DSPI slave ctar configuration structure.*/
288 typedef struct _dspi_slave_ctar_config
289 {
290 uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16.*/
291 dspi_clock_polarity_t cpol; /*!< Clock polarity. */
292 dspi_clock_phase_t cpha; /*!< Clock phase. */
293 /*!< Slave only supports MSB and does not support LSB.*/
294 } dspi_slave_ctar_config_t;
295 #endif
296
297 #if !(defined(FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT) && FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT)
298 /*! @brief DSPI slave configuration structure.*/
299 typedef struct _dspi_slave_config
300 {
301 dspi_ctar_selection_t whichCtar; /*!< The desired CTAR to use. */
302 dspi_slave_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */
303
304 bool enableContinuousSCK; /*!< CONT_SCKE, continuous SCK enable. Note that the continuous SCK is only
305 supported for CPHA = 1.*/
306 bool enableRxFifoOverWrite; /*!< ROOE, receive FIFO overflow overwrite enable. If ROOE = 0, the incoming
307 data is ignored and the data from the transfer that generated the overflow
308 is also ignored. If ROOE = 1, the incoming data is shifted to the
309 shift register. */
310 bool enableModifiedTimingFormat; /*!< Enables a modified transfer format to be used if true.*/
311 dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in the Modified Transfer
312 Format. It's valid only when CPHA=0. */
313 } dspi_slave_config_t;
314 #endif
315
316 /*!
317 * @brief Forward declaration of the @ref _dspi_master_handle typedefs.
318 */
319 typedef struct _dspi_master_handle dspi_master_handle_t; /*!< The master handle. */
320
321 #if !(defined(FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT) && FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT)
322 /*!
323 * @brief Forward declaration of the @ref _dspi_slave_handle typedefs.
324 */
325 typedef struct _dspi_slave_handle dspi_slave_handle_t; /*!< The slave handle. */
326 #endif
327
328 /*!
329 * @brief Completion callback function pointer type.
330 *
331 * @param base DSPI peripheral address.
332 * @param handle Pointer to the handle for the DSPI master.
333 * @param status Success or error code describing whether the transfer completed.
334 * @param userData Arbitrary pointer-dataSized value passed from the application.
335 */
336 typedef void (*dspi_master_transfer_callback_t)(SPI_Type *base,
337 dspi_master_handle_t *handle,
338 status_t status,
339 void *userData);
340
341 #if !(defined(FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT) && FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT)
342 /*!
343 * @brief Completion callback function pointer type.
344 *
345 * @param base DSPI peripheral address.
346 * @param handle Pointer to the handle for the DSPI slave.
347 * @param status Success or error code describing whether the transfer completed.
348 * @param userData Arbitrary pointer-dataSized value passed from the application.
349 */
350 typedef void (*dspi_slave_transfer_callback_t)(SPI_Type *base,
351 dspi_slave_handle_t *handle,
352 status_t status,
353 void *userData);
354 #endif
355
356 /*! @brief DSPI master/slave transfer structure.*/
357 typedef struct _dspi_transfer
358 {
359 const uint8_t *txData; /*!< Send buffer. */
360 uint8_t *rxData; /*!< Receive buffer. */
361 volatile size_t dataSize; /*!< Transfer bytes. */
362
363 uint32_t configFlags; /*!< Transfer transfer configuration flags. Set from @ref
364 _dspi_transfer_config_flag_for_master if the transfer is used for master or @ref
365 _dspi_transfer_config_flag_for_slave enumeration if the transfer is used for slave.*/
366 } dspi_transfer_t;
367
368 /*! @brief DSPI half-duplex(master) transfer structure */
369 typedef struct _dspi_half_duplex_transfer
370 {
371 const uint8_t *txData; /*!< Send buffer */
372 uint8_t *rxData; /*!< Receive buffer */
373 size_t txDataSize; /*!< Transfer bytes for transmit */
374 size_t rxDataSize; /*!< Transfer bytes */
375 uint32_t configFlags; /*!< Transfer configuration flags; set from @ref _dspi_transfer_config_flag_for_master. */
376 bool isPcsAssertInTransfer; /*!< If Pcs pin keep assert between transmit and receive. true for assert and false for
377 de-assert. */
378 bool isTransmitFirst; /*!< True for transmit first and false for receive first. */
379 } dspi_half_duplex_transfer_t;
380
381 /*! @brief DSPI master transfer handle structure used for transactional API. */
382 struct _dspi_master_handle
383 {
384 uint32_t bitsPerFrame; /*!< The desired number of bits per frame. */
385 volatile uint32_t command; /*!< The desired data command. */
386 volatile uint32_t lastCommand; /*!< The desired last data command. */
387
388 uint8_t fifoSize; /*!< FIFO dataSize. */
389
390 volatile bool
391 isPcsActiveAfterTransfer; /*!< Indicates whether the PCS signal is active after the last frame transfer.*/
392 volatile bool isThereExtraByte; /*!< Indicates whether there are extra bytes.*/
393
394 const uint8_t *volatile txData; /*!< Send buffer. */
395 uint8_t *volatile rxData; /*!< Receive buffer. */
396 volatile size_t remainingSendByteCount; /*!< A number of bytes remaining to send.*/
397 volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/
398 size_t totalByteCount; /*!< A number of transfer bytes*/
399
400 volatile uint8_t state; /*!< DSPI transfer state, see @ref _dspi_transfer_state.*/
401
402 dspi_master_transfer_callback_t callback; /*!< Completion callback. */
403 void *userData; /*!< Callback user data. */
404 };
405
406 #if !(defined(FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT) && FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT)
407 /*! @brief DSPI slave transfer handle structure used for the transactional API. */
408 struct _dspi_slave_handle
409 {
410 uint32_t bitsPerFrame; /*!< The desired number of bits per frame. */
411 volatile bool isThereExtraByte; /*!< Indicates whether there are extra bytes.*/
412
413 const uint8_t *volatile txData; /*!< Send buffer. */
414 uint8_t *volatile rxData; /*!< Receive buffer. */
415 volatile size_t remainingSendByteCount; /*!< A number of bytes remaining to send.*/
416 volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/
417 size_t totalByteCount; /*!< A number of transfer bytes*/
418
419 volatile uint8_t state; /*!< DSPI transfer state.*/
420
421 volatile uint32_t errorCount; /*!< Error count for slave transfer.*/
422
423 dspi_slave_transfer_callback_t callback; /*!< Completion callback. */
424 void *userData; /*!< Callback user data. */
425 };
426 #endif
427
428 /**********************************************************************************************************************
429 * API
430 *********************************************************************************************************************/
431 #if defined(__cplusplus)
432 extern "C" {
433 #endif /*_cplusplus*/
434
435 /*!
436 * @name Initialization and deinitialization
437 * @{
438 */
439
440 /*!
441 * @brief Initializes the DSPI master.
442 *
443 * This function initializes the DSPI master configuration. This is an example use case.
444 * @code
445 * dspi_master_config_t masterConfig;
446 * masterConfig.whichCtar = kDSPI_Ctar0;
447 * masterConfig.ctarConfig.baudRate = 500000000U;
448 * masterConfig.ctarConfig.bitsPerFrame = 8;
449 * masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
450 * masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge;
451 * masterConfig.ctarConfig.direction = kDSPI_MsbFirst;
452 * masterConfig.ctarConfig.pcsToSckDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ;
453 * masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ;
454 * masterConfig.ctarConfig.betweenTransferDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ;
455 * masterConfig.whichPcs = kDSPI_Pcs0;
456 * masterConfig.pcsActiveHighOrLow = kDSPI_PcsActiveLow;
457 * masterConfig.enableContinuousSCK = false;
458 * masterConfig.enableRxFifoOverWrite = false;
459 * masterConfig.enableModifiedTimingFormat = false;
460 * masterConfig.samplePoint = kDSPI_SckToSin0Clock;
461 * DSPI_MasterInit(base, &masterConfig, srcClock_Hz);
462 * @endcode
463 *
464 * @param base DSPI peripheral address.
465 * @param masterConfig Pointer to the structure @ref dspi_master_config_t.
466 * @param srcClock_Hz Module source input clock in Hertz.
467 */
468 void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz);
469
470 /*!
471 * @brief Sets the @ref dspi_master_config_t structure to default values.
472 *
473 * The purpose of this API is to get the configuration structure initialized for the DSPI_MasterInit().
474 * Users may use the initialized structure unchanged in the DSPI_MasterInit() or modify the structure
475 * before calling the DSPI_MasterInit().
476 * Example:
477 * @code
478 * dspi_master_config_t masterConfig;
479 * DSPI_MasterGetDefaultConfig(&masterConfig);
480 * @endcode
481 * @param masterConfig pointer to @ref dspi_master_config_t structure
482 */
483 void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig);
484
485 #if !(defined(FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT) && FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT)
486 /*!
487 * @brief DSPI slave configuration.
488 *
489 * This function initializes the DSPI slave configuration. This is an example use case.
490 * @code
491 * dspi_slave_config_t slaveConfig;
492 * slaveConfig->whichCtar = kDSPI_Ctar0;
493 * slaveConfig->ctarConfig.bitsPerFrame = 8;
494 * slaveConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
495 * slaveConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge;
496 * slaveConfig->enableContinuousSCK = false;
497 * slaveConfig->enableRxFifoOverWrite = false;
498 * slaveConfig->enableModifiedTimingFormat = false;
499 * slaveConfig->samplePoint = kDSPI_SckToSin0Clock;
500 * DSPI_SlaveInit(base, &slaveConfig);
501 * @endcode
502 *
503 * @param base DSPI peripheral address.
504 * @param slaveConfig Pointer to the structure @ref dspi_master_config_t.
505 */
506 void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig);
507 #endif
508
509 #if !(defined(FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT) && FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT)
510 /*!
511 * @brief Sets the @ref dspi_slave_config_t structure to a default value.
512 *
513 * The purpose of this API is to get the configuration structure initialized for the DSPI_SlaveInit().
514 * Users may use the initialized structure unchanged in the DSPI_SlaveInit() or modify the structure
515 * before calling the DSPI_SlaveInit().
516 * This is an example.
517 * @code
518 * dspi_slave_config_t slaveConfig;
519 * DSPI_SlaveGetDefaultConfig(&slaveConfig);
520 * @endcode
521 * @param slaveConfig Pointer to the @ref dspi_slave_config_t structure.
522 */
523 void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig);
524 #endif
525
526 /*!
527 * @brief De-initializes the DSPI peripheral. Call this API to disable the DSPI clock.
528 * @param base DSPI peripheral address.
529 */
530 void DSPI_Deinit(SPI_Type *base);
531
532 /*!
533 * @brief Enables the DSPI peripheral and sets the MCR MDIS to 0.
534 *
535 * @param base DSPI peripheral address.
536 * @param enable Pass true to enable module, false to disable module.
537 */
DSPI_Enable(SPI_Type * base,bool enable)538 static inline void DSPI_Enable(SPI_Type *base, bool enable)
539 {
540 if (enable)
541 {
542 base->MCR &= ~SPI_MCR_MDIS_MASK;
543 }
544 else
545 {
546 base->MCR |= SPI_MCR_MDIS_MASK;
547 }
548 }
549
550 /*!
551 *@}
552 */
553
554 /*!
555 * @name Status
556 * @{
557 */
558
559 /*!
560 * @brief Gets the DSPI status flag state.
561 * @param base DSPI peripheral address.
562 * @return DSPI status (in SR register).
563 */
DSPI_GetStatusFlags(SPI_Type * base)564 static inline uint32_t DSPI_GetStatusFlags(SPI_Type *base)
565 {
566 return (base->SR);
567 }
568
569 /*!
570 * @brief Clears the DSPI status flag.
571 *
572 * This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the
573 * desired status bit to clear. The list of status bits is defined in the <b>dspi_status_and_interrupt_request_t</b>.
574 * The function uses these bit positions in its algorithm to clear the desired flag state. This is an example.
575 * @code
576 * DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag|kDSPI_EndOfQueueFlag);
577 * @endcode
578 *
579 * @param base DSPI peripheral address.
580 * @param statusFlags The status flag used from the type dspi_flags.
581 */
DSPI_ClearStatusFlags(SPI_Type * base,uint32_t statusFlags)582 static inline void DSPI_ClearStatusFlags(SPI_Type *base, uint32_t statusFlags)
583 {
584 base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/
585 }
586
587 /*!
588 *@}
589 */
590
591 /*!
592 * @name Interrupts
593 * @{
594 */
595
596 /*!
597 * @brief Enables the DSPI interrupts.
598 *
599 * This function configures various interrupt masks of the DSPI. The parameters are a base and an interrupt mask.
600 * @note For Tx Fill and Rx FIFO drain requests, enable the interrupt request and disable the DMA request.
601 * Do not use this API(write to RSER register) while DSPI is in running state.
602 *
603 * @code
604 * DSPI_EnableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable );
605 * @endcode
606 *
607 * @param base DSPI peripheral address.
608 * @param mask The interrupt mask; use the enum @ref _dspi_interrupt_enable.
609 */
610 void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask);
611
612 /*!
613 * @brief Disables the DSPI interrupts.
614 *
615 * @code
616 * DSPI_DisableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable );
617 * @endcode
618 *
619 * @param base DSPI peripheral address.
620 * @param mask The interrupt mask; use the enum @ref _dspi_interrupt_enable.
621 */
DSPI_DisableInterrupts(SPI_Type * base,uint32_t mask)622 static inline void DSPI_DisableInterrupts(SPI_Type *base, uint32_t mask)
623 {
624 base->RSER &= ~mask;
625 }
626
627 /*!
628 *@}
629 */
630
631 /*!
632 * @name DMA Control
633 * @{
634 */
635
636 /*!
637 * @brief Enables the DSPI DMA request.
638 *
639 * This function configures the Rx and Tx DMA mask of the DSPI. The parameters are a base and a DMA mask.
640 * @code
641 * DSPI_EnableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable);
642 * @endcode
643 *
644 * @param base DSPI peripheral address.
645 * @param mask The interrupt mask; use the enum @ref _dspi_dma_enable.
646 */
DSPI_EnableDMA(SPI_Type * base,uint32_t mask)647 static inline void DSPI_EnableDMA(SPI_Type *base, uint32_t mask)
648 {
649 base->RSER |= mask;
650 }
651
652 /*!
653 * @brief Disables the DSPI DMA request.
654 *
655 * This function configures the Rx and Tx DMA mask of the DSPI. The parameters are a base and a DMA mask.
656 * @code
657 * SPI_DisableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable);
658 * @endcode
659 *
660 * @param base DSPI peripheral address.
661 * @param mask The interrupt mask; use the enum @ref _dspi_dma_enable.
662 */
DSPI_DisableDMA(SPI_Type * base,uint32_t mask)663 static inline void DSPI_DisableDMA(SPI_Type *base, uint32_t mask)
664 {
665 base->RSER &= ~mask;
666 }
667
668 /*!
669 * @brief Gets the DSPI master PUSHR data register address for the DMA operation.
670 *
671 * This function gets the DSPI master PUSHR data register address because this value is needed for the DMA operation.
672 *
673 * @param base DSPI peripheral address.
674 * @return The DSPI master PUSHR data register address.
675 */
DSPI_MasterGetTxRegisterAddress(SPI_Type * base)676 static inline uint32_t DSPI_MasterGetTxRegisterAddress(SPI_Type *base)
677 {
678 return (uint32_t) & (base->PUSHR);
679 }
680
681 /*!
682 * @brief Gets the DSPI slave PUSHR data register address for the DMA operation.
683 *
684 * This function gets the DSPI slave PUSHR data register address as this value is needed for the DMA operation.
685 *
686 * @param base DSPI peripheral address.
687 * @return The DSPI slave PUSHR data register address.
688 */
689 #if !(defined(FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT) && FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT)
DSPI_SlaveGetTxRegisterAddress(SPI_Type * base)690 static inline uint32_t DSPI_SlaveGetTxRegisterAddress(SPI_Type *base)
691 {
692 return (uint32_t) & (base->PUSHR_SLAVE);
693 }
694 #endif
695
696 /*!
697 * @brief Gets the DSPI POPR data register address for the DMA operation.
698 *
699 * This function gets the DSPI POPR data register address as this value is needed for the DMA operation.
700 *
701 * @param base DSPI peripheral address.
702 * @return The DSPI POPR data register address.
703 */
DSPI_GetRxRegisterAddress(SPI_Type * base)704 static inline uint32_t DSPI_GetRxRegisterAddress(SPI_Type *base)
705 {
706 return (uint32_t) & (base->POPR);
707 }
708
709 /*!
710 *@}
711 */
712
713 /*!
714 * @name Bus Operations
715 * @{
716 */
717 /*!
718 * @brief Get instance number for DSPI module.
719 *
720 * @param base DSPI peripheral base address.
721 */
722 uint32_t DSPI_GetInstance(SPI_Type *base);
723
724 /*!
725 * @brief Configures the DSPI for master or slave.
726 *
727 * @param base DSPI peripheral address.
728 * @param mode Mode setting (master or slave) of type @ref dspi_master_slave_mode_t.
729 */
DSPI_SetMasterSlaveMode(SPI_Type * base,dspi_master_slave_mode_t mode)730 static inline void DSPI_SetMasterSlaveMode(SPI_Type *base, dspi_master_slave_mode_t mode)
731 {
732 base->MCR = (base->MCR & (~SPI_MCR_MSTR_MASK)) | SPI_MCR_MSTR(mode);
733 }
734
735 /*!
736 * @brief Returns whether the DSPI module is in master mode.
737 *
738 * @param base DSPI peripheral address.
739 * @return Returns true if the module is in master mode or false if the module is in slave mode.
740 */
DSPI_IsMaster(SPI_Type * base)741 static inline bool DSPI_IsMaster(SPI_Type *base)
742 {
743 bool ismaster = false;
744 if (0U != ((base->MCR) & SPI_MCR_MSTR_MASK))
745 {
746 ismaster = true;
747 }
748 return ismaster;
749 }
750 /*!
751 * @brief Starts the DSPI transfers and clears HALT bit in MCR.
752 *
753 * This function sets the module to start data transfer in either master or slave mode.
754 *
755 * @param base DSPI peripheral address.
756 */
DSPI_StartTransfer(SPI_Type * base)757 static inline void DSPI_StartTransfer(SPI_Type *base)
758 {
759 base->MCR &= ~SPI_MCR_HALT_MASK;
760 }
761 /*!
762 * @brief Stops DSPI transfers and sets the HALT bit in MCR.
763 *
764 * This function stops data transfers in either master or slave modes.
765 *
766 * @param base DSPI peripheral address.
767 */
DSPI_StopTransfer(SPI_Type * base)768 static inline void DSPI_StopTransfer(SPI_Type *base)
769 {
770 base->MCR |= SPI_MCR_HALT_MASK;
771 }
772
773 /*!
774 * @brief Enables or disables the DSPI FIFOs.
775 *
776 * This function allows the caller to disable/enable the Tx and Rx FIFOs independently.
777 * @note To disable, pass in a logic 0 (false) for the particular FIFO configuration. To enable,
778 * pass in a logic 1 (true).
779 *
780 * @param base DSPI peripheral address.
781 * @param enableTxFifo Disables (false) the TX FIFO; Otherwise, enables (true) the TX FIFO
782 * @param enableRxFifo Disables (false) the RX FIFO; Otherwise, enables (true) the RX FIFO
783 */
DSPI_SetFifoEnable(SPI_Type * base,bool enableTxFifo,bool enableRxFifo)784 static inline void DSPI_SetFifoEnable(SPI_Type *base, bool enableTxFifo, bool enableRxFifo)
785 {
786 base->MCR = (base->MCR & (~(SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK))) |
787 SPI_MCR_DIS_TXF((false == enableTxFifo ? 1U : 0U)) | SPI_MCR_DIS_RXF((false == enableRxFifo ? 1U : 0U));
788 }
789
790 /*!
791 * @brief Flushes the DSPI FIFOs.
792 *
793 * @param base DSPI peripheral address.
794 * @param flushTxFifo Flushes (true) the Tx FIFO; Otherwise, does not flush (false) the Tx FIFO
795 * @param flushRxFifo Flushes (true) the Rx FIFO; Otherwise, does not flush (false) the Rx FIFO
796 */
DSPI_FlushFifo(SPI_Type * base,bool flushTxFifo,bool flushRxFifo)797 static inline void DSPI_FlushFifo(SPI_Type *base, bool flushTxFifo, bool flushRxFifo)
798 {
799 base->MCR = (base->MCR & (~(SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK))) |
800 SPI_MCR_CLR_TXF((true == flushTxFifo ? 1U : 0U)) | SPI_MCR_CLR_RXF((true == flushRxFifo ? 1U : 0U));
801 }
802
803 /*!
804 * @brief Configures the DSPI peripheral chip select polarity simultaneously.
805 * For example, PCS0 and PCS1 are set to active low and other PCS is set to active high. Note that the number of
806 * PCSs is specific to the device.
807 * @code
808 * DSPI_SetAllPcsPolarity(base, kDSPI_Pcs0ActiveLow | kDSPI_Pcs1ActiveLow);
809 @endcode
810 * @param base DSPI peripheral address.
811 * @param mask The PCS polarity mask; use the enum @ref _dspi_pcs_polarity.
812 */
DSPI_SetAllPcsPolarity(SPI_Type * base,uint32_t mask)813 static inline void DSPI_SetAllPcsPolarity(SPI_Type *base, uint32_t mask)
814 {
815 base->MCR = (base->MCR & ~SPI_MCR_PCSIS_MASK) | SPI_MCR_PCSIS(mask);
816 }
817
818 /*!
819 * @brief Sets the DSPI baud rate in bits per second.
820 *
821 * This function takes in the desired baudRate_Bps (baud rate) and calculates the nearest possible baud rate without
822 * exceeding the desired baud rate, and returns the calculated baud rate in bits-per-second. It requires that the
823 * caller also provide the frequency of the module source clock (in Hertz).
824 *
825 * @param base DSPI peripheral address.
826 * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of the type @ref dspi_ctar_selection_t
827 * @param baudRate_Bps The desired baud rate in bits per second
828 * @param srcClock_Hz Module source input clock in Hertz
829 * @return The actual calculated baud rate
830 */
831 uint32_t DSPI_MasterSetBaudRate(SPI_Type *base,
832 dspi_ctar_selection_t whichCtar,
833 uint32_t baudRate_Bps,
834 uint32_t srcClock_Hz);
835
836 /*!
837 * @brief Manually configures the delay prescaler and scaler for a particular CTAR.
838 *
839 * This function configures the PCS to SCK delay pre-scalar (PcsSCK) and scalar (CSSCK), after SCK delay pre-scalar
840 * (PASC) and scalar (ASC), and the delay after transfer pre-scalar (PDT) and scalar (DT).
841 *
842 * These delay names are available in the type @ref dspi_delay_type_t.
843 *
844 * The user passes the delay to the configuration along with the prescaler and scaler value.
845 * This allows the user to directly set the prescaler/scaler values if pre-calculated or
846 * to manually increment either value.
847 *
848 * @param base DSPI peripheral address.
849 * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type @ref dspi_ctar_selection_t.
850 * @param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3).
851 * @param scaler The scaler delay value (can be any integer between 0 to 15).
852 * @param whichDelay The desired delay to configure; must be of type @ref dspi_delay_type_t
853 */
854 void DSPI_MasterSetDelayScaler(
855 SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay);
856
857 /*!
858 * @brief Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds.
859 *
860 * This function calculates the values for the following.
861 * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or
862 * After SCK delay pre-scalar (PASC) and scalar (ASC), or
863 * Delay after transfer pre-scalar (PDT) and scalar (DT).
864 *
865 * These delay names are available in the type @ref dspi_delay_type_t.
866 *
867 * The user passes which delay to configure along with the desired delay value in nanoseconds. The function
868 * calculates the values needed for the prescaler and scaler. Note that returning the calculated delay as an exact
869 * delay match may not be possible. In this case, the closest match is calculated without going below the desired
870 * delay value input.
871 * It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum
872 * supported delay is returned. The higher-level peripheral driver alerts the user of an out of range delay
873 * input.
874 *
875 * @param base DSPI peripheral address.
876 * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type @ref dspi_ctar_selection_t.
877 * @param whichDelay The desired delay to configure, must be of type @ref dspi_delay_type_t
878 * @param srcClock_Hz Module source input clock in Hertz
879 * @param delayTimeInNanoSec The desired delay value in nanoseconds.
880 * @return The actual calculated delay value.
881 */
882 uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base,
883 dspi_ctar_selection_t whichCtar,
884 dspi_delay_type_t whichDelay,
885 uint32_t srcClock_Hz,
886 uint32_t delayTimeInNanoSec);
887
888 /*!
889 * @brief Writes data into the data buffer for master mode.
890 *
891 * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
892 * provides characteristics of the data, such as the optional continuous chip select
893 * operation between transfers, the desired Clock and Transfer Attributes register to use for the
894 * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
895 * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
896 * sending the first frame of a data packet). This is an example.
897 * @code
898 * dspi_command_data_config_t commandConfig;
899 * commandConfig.isPcsContinuous = true;
900 * commandConfig.whichCtar = kDSPICtar0;
901 * commandConfig.whichPcs = kDSPIPcs0;
902 * commandConfig.clearTransferCount = false;
903 * commandConfig.isEndOfQueue = false;
904 * DSPI_MasterWriteData(base, &commandConfig, dataWord);
905 @endcode
906 *
907 * @param base DSPI peripheral address.
908 * @param command Pointer to the command structure.
909 * @param data The data word to be sent.
910 */
DSPI_MasterWriteData(SPI_Type * base,dspi_command_data_config_t * command,uint16_t data)911 static inline void DSPI_MasterWriteData(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data)
912 {
913 base->PUSHR = SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) |
914 SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) |
915 SPI_PUSHR_CTCNT(command->clearTransferCount) | SPI_PUSHR_TXDATA(data);
916 }
917
918 /*!
919 * @brief Sets the @ref dspi_command_data_config_t structure to default values.
920 *
921 * The purpose of this API is to get the configuration structure initialized for use in the
922 * <b>DSPI_MasterWrite_xx()</b>. Users may use the initialized structure unchanged in the DSPI_MasterWrite_xx() or
923 * modify the structure before calling the DSPI_MasterWrite_xx(). This is an example.
924 * @code
925 * dspi_command_data_config_t command;
926 * DSPI_GetDefaultDataCommandConfig(&command);
927 * @endcode
928 * @param command Pointer to the @ref dspi_command_data_config_t structure.
929 */
930 void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command);
931
932 /*!
933 * @brief Writes data into the data buffer master mode and waits till complete to return.
934 *
935 * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
936 * provides characteristics of the data, such as the optional continuous chip select
937 * operation between transfers, the desired Clock and Transfer Attributes register to use for the
938 * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
939 * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
940 * sending the first frame of a data packet). This is an example.
941 * @code
942 * dspi_command_config_t commandConfig;
943 * commandConfig.isPcsContinuous = true;
944 * commandConfig.whichCtar = kDSPICtar0;
945 * commandConfig.whichPcs = kDSPIPcs1;
946 * commandConfig.clearTransferCount = false;
947 * commandConfig.isEndOfQueue = false;
948 * DSPI_MasterWriteDataBlocking(base, &commandConfig, dataWord);
949 * @endcode
950 *
951 * @note This function does not return until after the transmit is complete. Also note that the DSPI must be
952 * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). Because the SPI is a synchronous protocol,
953 * the received data is available when the transmit completes.
954 *
955 * @param base DSPI peripheral address.
956 * @param command Pointer to the command structure.
957 * @param data The data word to be sent.
958 */
959 void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data);
960
961 /*!
962 * @brief Returns the DSPI command word formatted to the PUSHR data register bit field.
963 *
964 * This function allows the caller to pass in the data command structure and returns the command word formatted
965 * according to the DSPI PUSHR register bit field placement. The user can then "OR" the returned command word with the
966 * desired data to send and use the function <b>DSPI_HAL_WriteCommandDataMastermode</b> or
967 * <b>DSPI_HAL_WriteCommandDataMastermodeBlocking</b> to write the entire 32-bit command data word to the PUSHR. This
968 * helps improve performance in cases where the command structure is constant. For example, the user calls this function
969 * before starting a transfer to generate the command word. When they are ready to transmit the data, they OR
970 * this formatted command word with the desired data to transmit. This process increases transmit performance when
971 * compared to calling send functions, such as <b>DSPI_HAL_WriteDataMastermode</b>, which format the command word each
972 * time a data word is to be sent.
973 *
974 * @param command Pointer to the command structure.
975 * @return The command word formatted to the PUSHR data register bit field.
976 */
DSPI_MasterGetFormattedCommand(dspi_command_data_config_t * command)977 static inline uint32_t DSPI_MasterGetFormattedCommand(dspi_command_data_config_t *command)
978 {
979 /* Format the 16-bit command word according to the PUSHR data register bit field*/
980 return (uint32_t)(SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) |
981 SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) |
982 SPI_PUSHR_CTCNT(command->clearTransferCount));
983 }
984
985 /*!
986 * @brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data
987 * buffer master mode and waits till complete to return.
988 *
989 * In this function, the user must append the 16-bit data to the 16-bit command information and then provide the total
990 * 32-bit word
991 * as the data to send.
992 * The command portion provides characteristics of the data, such as the optional continuous chip select operation
993 * between transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the
994 * desired PCS
995 * signal to use for the data transfer, whether the current transfer is the last in the queue, and whether to clear the
996 * transfer count (normally needed when sending the first frame of a data packet). The user is responsible for
997 * appending this command with the data to send. This is an example:
998 * @code
999 * dataWord = <16-bit command> | <16-bit data>;
1000 * DSPI_MasterWriteCommandDataBlocking(base, dataWord);
1001 * @endcode
1002 *
1003 * @note This function does not return until after the transmit is complete. Also note that the DSPI must be
1004 * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0).
1005 * Because the SPI is a synchronous protocol, the received data is available when the transmit completes.
1006 *
1007 * For a blocking polling transfer, see methods below.
1008 * <table>
1009 * <tr><th>Option 1
1010 * <tr><td>uint32_t command_to_send = DSPI_MasterGetFormattedCommand(&command);
1011 * <tr><td>uint32_t data0 = command_to_send | data_need_to_send_0;
1012 * <tr><td>uint32_t data1 = command_to_send | data_need_to_send_1;
1013 * <tr><td>uint32_t data2 = command_to_send | data_need_to_send_2;
1014 * <tr><td>
1015 * <tr><td>DSPI_MasterWriteCommandDataBlocking(base,data0);
1016 * <tr><td>DSPI_MasterWriteCommandDataBlocking(base,data1);
1017 * <tr><td>DSPI_MasterWriteCommandDataBlocking(base,data2);
1018 * </table>
1019 *
1020 * <table>
1021 * <tr><th>Option 2
1022 * <tr><td>DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_0);
1023 * <tr><td>DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_1);
1024 * <tr><td>DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_2);
1025 * </table>
1026 *
1027 * @param base DSPI peripheral address.
1028 * @param data The data word (command and data combined) to be sent.
1029 */
1030 void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data);
1031
1032 #if !(defined(FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT) && FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT)
1033 /*!
1034 * @brief Writes data into the data buffer in slave mode.
1035 *
1036 * In slave mode, up to 16-bit words may be written.
1037 *
1038 * @param base DSPI peripheral address.
1039 * @param data The data to send.
1040 */
DSPI_SlaveWriteData(SPI_Type * base,uint32_t data)1041 static inline void DSPI_SlaveWriteData(SPI_Type *base, uint32_t data)
1042 {
1043 base->PUSHR_SLAVE = data;
1044 }
1045 #endif
1046
1047 #if !(defined(FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT) && FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT)
1048 /*!
1049 * @brief Writes data into the data buffer in slave mode, waits till data was transmitted, and returns.
1050 *
1051 * In slave mode, up to 16-bit words may be written. The function first clears the transmit complete flag, writes data
1052 * into data register, and finally waits until the data is transmitted.
1053 *
1054 * @param base DSPI peripheral address.
1055 * @param data The data to send.
1056 */
1057 void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data);
1058 #endif
1059
1060 /*!
1061 * @brief Reads data from the data buffer.
1062 *
1063 * @param base DSPI peripheral address.
1064 * @return The data from the read data buffer.
1065 */
DSPI_ReadData(SPI_Type * base)1066 static inline uint32_t DSPI_ReadData(SPI_Type *base)
1067 {
1068 return (base->POPR);
1069 }
1070
1071 /*!
1072 * @brief Set up the dummy data.
1073 *
1074 * @param base DSPI peripheral address.
1075 * @param dummyData Data to be transferred when tx buffer is NULL.
1076 */
1077 void DSPI_SetDummyData(SPI_Type *base, uint8_t dummyData);
1078
1079 /*!
1080 *@}
1081 */
1082
1083 /*!
1084 * @name Transactional APIs
1085 * @{
1086 */
1087
1088 /*!
1089 * @brief Initializes the DSPI master handle.
1090 *
1091 * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a
1092 * specified DSPI instance, call this API once to get the initialized handle.
1093 *
1094 * @param base DSPI peripheral base address.
1095 * @param handle DSPI handle pointer to @ref _dspi_master_handle.
1096 * @param callback DSPI callback.
1097 * @param userData Callback function parameter.
1098 */
1099 void DSPI_MasterTransferCreateHandle(SPI_Type *base,
1100 dspi_master_handle_t *handle,
1101 dspi_master_transfer_callback_t callback,
1102 void *userData);
1103
1104 /*!
1105 * @brief DSPI master transfer data using polling.
1106 *
1107 * This function transfers data using polling. This is a blocking function, which does not return until all transfers
1108 * have been completed.
1109 *
1110 * @param base DSPI peripheral base address.
1111 * @param transfer Pointer to the @ref dspi_transfer_t structure.
1112 * @return status of status_t.
1113 */
1114 status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer);
1115
1116 /*!
1117 * @brief DSPI master transfer data using interrupts.
1118 *
1119 * This function transfers data using interrupts. This is a non-blocking function, which returns right away. When all
1120 * data is transferred, the callback function is called.
1121
1122 * @param base DSPI peripheral base address.
1123 * @param handle Pointer to the @ref _dspi_master_handle structure which stores the transfer state.
1124 * @param transfer Pointer to the @ref dspi_transfer_t structure.
1125 * @return status of status_t.
1126 */
1127 status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer);
1128
1129 /*!
1130 * @brief Transfers a block of data using a polling method.
1131 *
1132 * This function will do a half-duplex transfer for DSPI master, This is a blocking function,
1133 * which does not retuen until all transfer have been completed. And data transfer will be half-duplex,
1134 * users can set transmit first or receive first.
1135 *
1136 * @param base DSPI base pointer
1137 * @param xfer pointer to @ref dspi_half_duplex_transfer_t structure
1138 * @return status of status_t.
1139 */
1140 status_t DSPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, dspi_half_duplex_transfer_t *xfer);
1141
1142 /*!
1143 * @brief Performs a non-blocking DSPI interrupt transfer.
1144 *
1145 * This function transfers data using interrupts, the transfer mechanism is half-duplex. This is a non-blocking
1146 * function,
1147 * which returns right away. When all data is transferred, the callback function is called.
1148 *
1149 * @param base DSPI peripheral base address.
1150 * @param handle pointer to @ref _dspi_master_handle structure which stores the transfer state
1151 * @param xfer pointer to @ref dspi_half_duplex_transfer_t structure
1152 * @return status of status_t.
1153 */
1154 status_t DSPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base,
1155 dspi_master_handle_t *handle,
1156 dspi_half_duplex_transfer_t *xfer);
1157
1158 /*!
1159 * @brief Gets the master transfer count.
1160 *
1161 * This function gets the master transfer count.
1162 *
1163 * @param base DSPI peripheral base address.
1164 * @param handle Pointer to the @ref _dspi_master_handle structure which stores the transfer state.
1165 * @param count The number of bytes transferred by using the non-blocking transaction.
1166 * @return status of status_t.
1167 */
1168 status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handle, size_t *count);
1169
1170 /*!
1171 * @brief DSPI master aborts a transfer using an interrupt.
1172 *
1173 * This function aborts a transfer using an interrupt.
1174 *
1175 * @param base DSPI peripheral base address.
1176 * @param handle Pointer to the @ref _dspi_master_handle structure which stores the transfer state.
1177 */
1178 void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle);
1179
1180 /*!
1181 * @brief DSPI Master IRQ handler function.
1182 *
1183 * This function processes the DSPI transmit and receive IRQ.
1184
1185 * @param base DSPI peripheral base address.
1186 * @param handle Pointer to the @ref _dspi_master_handle structure which stores the transfer state.
1187 */
1188 void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle);
1189
1190 #if !(defined(FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT) && FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT)
1191 /*!
1192 * @brief Initializes the DSPI slave handle.
1193 *
1194 * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a
1195 * specified DSPI instance, call this API once to get the initialized handle.
1196 *
1197 * @param handle DSPI handle pointer to the @ref _dspi_slave_handle.
1198 * @param base DSPI peripheral base address.
1199 * @param callback DSPI callback.
1200 * @param userData Callback function parameter.
1201 */
1202 void DSPI_SlaveTransferCreateHandle(SPI_Type *base,
1203 dspi_slave_handle_t *handle,
1204 dspi_slave_transfer_callback_t callback,
1205 void *userData);
1206 #endif
1207
1208 #if !(defined(FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT) && FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT)
1209 /*!
1210 * @brief DSPI slave transfers data using an interrupt.
1211 *
1212 * This function transfers data using an interrupt. This is a non-blocking function, which returns right away. When all
1213 * data is transferred, the callback function is called.
1214 *
1215 * @param base DSPI peripheral base address.
1216 * @param handle Pointer to the @ref _dspi_slave_handle structure which stores the transfer state.
1217 * @param transfer Pointer to the @ref dspi_transfer_t structure.
1218 * @return status of status_t.
1219 */
1220 status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer);
1221 #endif
1222
1223 #if !(defined(FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT) && FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT)
1224 /*!
1225 * @brief Gets the slave transfer count.
1226 *
1227 * This function gets the slave transfer count.
1228 *
1229 * @param base DSPI peripheral base address.
1230 * @param handle Pointer to the @ref _dspi_master_handle structure which stores the transfer state.
1231 * @param count The number of bytes transferred by using the non-blocking transaction.
1232 * @return status of status_t.
1233 */
1234 status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle, size_t *count);
1235 #endif
1236
1237 #if !(defined(FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT) && FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT)
1238 /*!
1239 * @brief DSPI slave aborts a transfer using an interrupt.
1240 *
1241 * This function aborts a transfer using an interrupt.
1242 *
1243 * @param base DSPI peripheral base address.
1244 * @param handle Pointer to the @ref _dspi_slave_handle structure which stores the transfer state.
1245 */
1246 void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle);
1247 #endif
1248
1249 #if !(defined(FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT) && FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT)
1250 /*!
1251 * @brief DSPI Master IRQ handler function.
1252 *
1253 * This function processes the DSPI transmit and receive IRQ.
1254 *
1255 * @param base DSPI peripheral base address.
1256 * @param handle Pointer to the @ref _dspi_slave_handle structure which stores the transfer state.
1257 */
1258 void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle);
1259 #endif
1260
1261 /*!
1262 * brief Dummy data for each instance.
1263 *
1264 * The purpose of this API is to avoid MISRA rule8.5 : Multiple declarations of
1265 * externally-linked object or function @ref g_dspiDummyData.
1266 *
1267 * param base DSPI peripheral base address.
1268 */
1269 uint8_t DSPI_GetDummyDataInstance(SPI_Type *base);
1270
1271 /*!
1272 *@}
1273 */
1274
1275 #if defined(__cplusplus)
1276 }
1277 #endif /*_cplusplus*/
1278 /*!
1279 *@}
1280 */
1281
1282 #endif /*FSL_DSPI_H_*/
1283
