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Searched refs:DPHYESCTXCLKDIV_OFFSET (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_clock.h600 #define DPHYESCTXCLKDIV_OFFSET 0x780 macro
995 …kCLOCK_DivDphyEscTxClk = CLKCTL0_TUPLE_MUXA(DPHYESCTXCLKDIV_OFFSET, 0), /*!< Dphy Esc Tx Clk Divi…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_clock.h600 #define DPHYESCTXCLKDIV_OFFSET 0x780 macro
995 …kCLOCK_DivDphyEscTxClk = CLKCTL0_TUPLE_MUXA(DPHYESCTXCLKDIV_OFFSET, 0), /*!< Dphy Esc Tx Clk Divi…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_clock.h600 #define DPHYESCTXCLKDIV_OFFSET 0x780 macro
995 …kCLOCK_DivDphyEscTxClk = CLKCTL0_TUPLE_MUXA(DPHYESCTXCLKDIV_OFFSET, 0), /*!< Dphy Esc Tx Clk Divi…