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Searched refs:DPHYESCRXCLKDIV_OFFSET (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_clock.h599 #define DPHYESCRXCLKDIV_OFFSET 0x77C macro
994 …kCLOCK_DivDphyEscRxClk = CLKCTL0_TUPLE_MUXA(DPHYESCRXCLKDIV_OFFSET, 0), /*!< Dphy Esc Rx Clk Divi…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_clock.h599 #define DPHYESCRXCLKDIV_OFFSET 0x77C macro
994 …kCLOCK_DivDphyEscRxClk = CLKCTL0_TUPLE_MUXA(DPHYESCRXCLKDIV_OFFSET, 0), /*!< Dphy Esc Rx Clk Divi…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_clock.h599 #define DPHYESCRXCLKDIV_OFFSET 0x77C macro
994 …kCLOCK_DivDphyEscRxClk = CLKCTL0_TUPLE_MUXA(DPHYESCRXCLKDIV_OFFSET, 0), /*!< Dphy Esc Rx Clk Divi…