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Searched refs:DPHYCLKDIV_OFFSET (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_clock.h598 #define DPHYCLKDIV_OFFSET 0x774 macro
993 … kCLOCK_DivDphyClk = CLKCTL0_TUPLE_MUXA(DPHYCLKDIV_OFFSET, 0), /*!< Dphy Clk Divider. */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_clock.h598 #define DPHYCLKDIV_OFFSET 0x774 macro
993 … kCLOCK_DivDphyClk = CLKCTL0_TUPLE_MUXA(DPHYCLKDIV_OFFSET, 0), /*!< Dphy Clk Divider. */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_clock.h598 #define DPHYCLKDIV_OFFSET 0x774 macro
993 … kCLOCK_DivDphyClk = CLKCTL0_TUPLE_MUXA(DPHYCLKDIV_OFFSET, 0), /*!< Dphy Clk Divider. */